Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	250805404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

179219273

1

T1

4

T2

342800

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	222226323	1			T1	1		T2	440293		T3	1
values[0x0]	99812309	1			T1	9		T2	211638		T3	26
values[0x1]	107986045	1			T1	4		T2	226564		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	194967934	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

235056743

1

T1

4

T2

458399

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1309294	1			T2	3543		T7	121		T8	8556
valid_sources[0x01]	1763647	1			T2	3414		T3	1		T7	189
valid_sources[0x02]	1928276	1			T2	3371		T7	166		T8	7460
valid_sources[0x03]	1310622	1			T2	3335		T7	171		T8	8150
valid_sources[0x04]	1438282	1			T2	3399		T7	232		T8	7709
valid_sources[0x05]	1370788	1			T2	3263		T7	187		T8	8096
valid_sources[0x06]	1306644	1			T2	3424		T7	195		T8	8694
valid_sources[0x07]	1693040	1			T2	3453		T3	1		T7	174
valid_sources[0x08]	1310778	1			T2	3457		T3	1		T7	132
valid_sources[0x09]	1310231	1			T2	3431		T7	177		T8	8412
valid_sources[0x0a]	1307054	1			T2	3441		T7	159		T8	7919
valid_sources[0x0b]	2191188	1			T2	3429		T7	168		T8	8220
valid_sources[0x0c]	1974955	1			T2	3551		T7	192		T8	7700
valid_sources[0x0d]	1305149	1			T2	3453		T7	178		T8	7020
valid_sources[0x0e]	1310846	1			T2	3428		T7	128		T8	7798
valid_sources[0x0f]	1308223	1			T2	3295		T7	133		T8	8748
valid_sources[0x10]	1305954	1			T2	3418		T7	187		T8	8218
valid_sources[0x11]	1317201	1			T2	3419		T7	235		T8	7149
valid_sources[0x12]	1314003	1			T2	3391		T7	178		T8	6702
valid_sources[0x13]	1305562	1			T2	3389		T7	217		T8	7276
valid_sources[0x14]	1361043	1			T2	3497		T7	235		T8	8071
valid_sources[0x15]	1448454	1			T2	3513		T7	152		T8	6544
valid_sources[0x16]	1316453	1			T2	3377		T7	181		T8	8068
valid_sources[0x17]	1313358	1			T2	3397		T3	4		T7	229
valid_sources[0x18]	1308165	1			T2	3457		T7	106		T8	7883
valid_sources[0x19]	1307106	1			T2	3389		T7	110		T8	8266
valid_sources[0x1a]	1307195	1			T2	3389		T7	157		T8	8121
valid_sources[0x1b]	1306805	1			T2	3443		T7	138		T8	8105
valid_sources[0x1c]	1392151	1			T2	3517		T7	150		T8	7522
valid_sources[0x1d]	1306763	1			T2	3398		T7	113		T8	6732
valid_sources[0x1e]	1965402	1			T2	3340		T3	1		T7	146
valid_sources[0x1f]	1499959	1			T2	3420		T7	154		T8	8141
valid_sources[0x20]	1313058	1			T2	3451		T7	179		T8	7722
valid_sources[0x21]	1307057	1			T2	3463		T7	223		T8	7623
valid_sources[0x22]	2202572	1			T2	3355		T3	2		T7	222
valid_sources[0x23]	1446534	1			T2	3559		T7	152		T8	7531
valid_sources[0x24]	1348057	1			T2	3597		T7	201		T8	8036
valid_sources[0x25]	1312602	1			T2	3367		T7	162		T8	7903
valid_sources[0x26]	3658380	1			T2	3449		T3	1		T7	205
valid_sources[0x27]	1755974	1			T2	3500		T7	139		T8	7703
valid_sources[0x28]	1304383	1			T2	3279		T7	202		T8	6917
valid_sources[0x29]	1448366	1			T2	3523		T7	151		T8	8465
valid_sources[0x2a]	1308373	1			T2	3377		T7	126		T8	7213
valid_sources[0x2b]	1310875	1			T2	3458		T7	187		T8	8163
valid_sources[0x2c]	2671492	1			T2	3468		T7	168		T8	7633
valid_sources[0x2d]	1401183	1			T2	3630		T7	218		T8	7606
valid_sources[0x2e]	1338413	1			T2	3403		T7	183		T8	7822
valid_sources[0x2f]	1333696	1			T2	3486		T7	165		T8	7753
valid_sources[0x30]	2383651	1			T2	3435		T7	200		T8	8242
valid_sources[0x31]	1312657	1			T2	3464		T7	162		T8	7732
valid_sources[0x32]	1953129	1			T2	3441		T7	177		T8	7236
valid_sources[0x33]	1307408	1			T2	3358		T7	190		T8	7764
valid_sources[0x34]	1304285	1			T2	3497		T7	151		T8	7877
valid_sources[0x35]	1309190	1			T2	3386		T7	191		T8	7088
valid_sources[0x36]	1307307	1			T2	3504		T7	210		T8	9152
valid_sources[0x37]	1306019	1			T2	3540		T7	124		T8	7047
valid_sources[0x38]	2158173	1			T2	3363		T7	229		T8	7199
valid_sources[0x39]	3650661	1			T2	3467		T7	207		T8	7912
valid_sources[0x3a]	1308807	1			T2	3368		T7	172		T8	7596
valid_sources[0x3b]	1315540	1			T2	3382		T7	194		T8	7474
valid_sources[0x3c]	1306832	1			T2	3384		T7	197		T8	7599
valid_sources[0x3d]	3311771	1			T2	3493		T7	175		T8	7254
valid_sources[0x3e]	1729856	1			T2	3566		T3	1		T7	191
valid_sources[0x3f]	2057046	1			T2	3495		T7	141		T8	7129
valid_sources[0x40]	1304032	1			T2	3414		T7	161		T8	8363
valid_sources[0x41]	1310823	1			T2	3462		T3	1		T7	229
valid_sources[0x42]	1956202	1			T2	3427		T7	228		T8	7623
valid_sources[0x43]	1305680	1			T2	3280		T7	167		T8	8320
valid_sources[0x44]	1305612	1			T2	3466		T7	262		T8	7580
valid_sources[0x45]	1951919	1			T2	3387		T7	177		T8	7943
valid_sources[0x46]	1306692	1			T2	3343		T3	1		T7	138
valid_sources[0x47]	1303195	1			T2	3459		T7	98		T8	7322
valid_sources[0x48]	1308606	1			T2	3473		T7	128		T8	8620
valid_sources[0x49]	1317304	1			T2	3510		T7	175		T8	7250
valid_sources[0x4a]	1312011	1			T2	3549		T3	1		T7	140
valid_sources[0x4b]	1304994	1			T2	3317		T7	166		T8	6798
valid_sources[0x4c]	1311364	1			T2	3445		T7	126		T8	7271
valid_sources[0x4d]	2160368	1			T2	3518		T7	162		T8	8165
valid_sources[0x4e]	1307914	1			T2	3359		T7	201		T8	9011
valid_sources[0x4f]	1309658	1			T2	3469		T7	149		T8	7289
valid_sources[0x50]	1307132	1			T2	3454		T3	1		T7	169
valid_sources[0x51]	1303109	1			T2	3472		T7	200		T8	8103
valid_sources[0x52]	1310368	1			T2	3467		T7	141		T8	7351
valid_sources[0x53]	1508063	1			T2	3456		T7	218		T8	7769
valid_sources[0x54]	1311667	1			T2	3393		T7	137		T8	7302
valid_sources[0x55]	1309762	1			T2	3505		T7	170		T8	7769
valid_sources[0x56]	2225247	1			T2	3524		T7	249		T8	6711
valid_sources[0x57]	2193841	1			T2	3369		T7	239		T8	8570
valid_sources[0x58]	1309949	1			T2	3334		T7	129		T8	9149
valid_sources[0x59]	1303677	1			T2	3443		T7	155		T8	8353
valid_sources[0x5a]	2176578	1			T2	3432		T7	176		T8	7683
valid_sources[0x5b]	1765089	1			T2	3469		T7	175		T8	7565
valid_sources[0x5c]	1301050	1			T2	3516		T7	180		T8	7728
valid_sources[0x5d]	1310392	1			T2	3375		T3	3		T7	153
valid_sources[0x5e]	1307338	1			T2	3427		T3	1		T7	164
valid_sources[0x5f]	2255943	1			T2	3482		T7	185		T8	8364
valid_sources[0x60]	2206323	1			T1	2		T2	3327		T3	2
valid_sources[0x61]	1309718	1			T2	3433		T7	157		T8	8911
valid_sources[0x62]	3331162	1			T2	3388		T7	143		T8	6573
valid_sources[0x63]	1305865	1			T2	3364		T7	154		T8	8412
valid_sources[0x64]	1303489	1			T2	3396		T7	188		T8	8857
valid_sources[0x65]	3279752	1			T2	3430		T7	223		T8	8568
valid_sources[0x66]	1952617	1			T2	3410		T7	150		T8	6983
valid_sources[0x67]	1308376	1			T2	3447		T7	151		T8	6657
valid_sources[0x68]	1305333	1			T2	3403		T7	155		T8	8921
valid_sources[0x69]	2594012	1			T2	3445		T7	120		T8	8121
valid_sources[0x6a]	1315124	1			T2	3479		T7	192		T8	7101
valid_sources[0x6b]	1313593	1			T2	3412		T7	180		T8	7978
valid_sources[0x6c]	1325752	1			T1	5		T2	3315		T7	188
valid_sources[0x6d]	1304531	1			T2	3371		T3	1		T7	163
valid_sources[0x6e]	2413779	1			T2	3374		T3	1		T7	181
valid_sources[0x6f]	1973939	1			T2	3320		T7	175		T8	8168
valid_sources[0x70]	1324587	1			T2	3445		T3	1		T7	180
valid_sources[0x71]	1304465	1			T2	3349		T3	3		T7	138
valid_sources[0x72]	1396753	1			T2	3418		T3	2		T7	195
valid_sources[0x73]	1310736	1			T2	3312		T7	188		T8	7062
valid_sources[0x74]	1780651	1			T2	3449		T7	143		T8	8188
valid_sources[0x75]	1312697	1			T2	3408		T7	141		T8	7025
valid_sources[0x76]	2234232	1			T2	3389		T7	156		T8	7198
valid_sources[0x77]	2161826	1			T2	3498		T7	146		T8	8681
valid_sources[0x78]	2206107	1			T2	3366		T3	1		T7	212
valid_sources[0x79]	1309846	1			T2	3402		T7	165		T8	8457
valid_sources[0x7a]	1306345	1			T2	3381		T7	162		T8	8944
valid_sources[0x7b]	1316093	1			T2	3530		T7	107		T8	8124
valid_sources[0x7c]	3287263	1			T2	3419		T7	197		T8	7135
valid_sources[0x7d]	1846274	1			T2	3402		T7	173		T8	7458
valid_sources[0x7e]	1312442	1			T2	3426		T7	146		T8	6872
valid_sources[0x7f]	1307821	1			T2	3442		T3	1		T7	111
valid_sources[0x80]	3271262	1			T2	3426		T7	212		T8	7619

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69428817

1

T2

114731

T3

1

T7

14478

values[0x0]

all_enables

biggest_size

58988897

1

T1

4

T2

123334

T3

6

values[0x1]

all_enables

biggest_size

50801559

1

T2

104735

T3

2

T7

3770