Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

254028366

1

T1

10

T2

535695

T3

40

full_word

179422558

1

T1

4

T2

342800

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	433450644	1			T1	14		T2	878495		T3	49
auto[TlIntgErrCmd]	101	1			T130	5		T131	5		T132	6
auto[TlIntgErrData]	86	1			T130	2		T131	7		T132	3
auto[TlIntgErrBoth]	93	1			T130	3		T131	8		T132	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

222852368

1

T1

1

T2

440293

T3

1

auto[1]

210598556

1

T1

13

T2

438202

T3

48

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153372514	1			T1	1		T2	325562		T7	15725
auto[TlIntgErrNone]	partial	auto[1]	100655592	1			T1	9		T2	210133		T3	40
auto[TlIntgErrNone]	full_word	auto[0]	69479724	1			T2	114731		T3	1		T7	14478
auto[TlIntgErrNone]	full_word	auto[1]	109942814	1			T1	4		T2	228069		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T130	2		T131	4		T132	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T130	3		T131	1		T132	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T132	1		T179	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T183	1		T181	1		T184	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T130	1		T131	5		T132	2
auto[TlIntgErrData]	partial	auto[1]	33	1			T130	1		T131	2		T132	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T184	1		T180	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T183	1		T185	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T130	1		T131	2		T186	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T130	2		T131	6		T164	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T183	1		T182	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T132	1		T179	1		T187	1