Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	745483	0	0
entropy_period_rd_A	2147483647	1737	0	0
intr_enable_rd_A	2147483647	2695	0	0
prefix_0_rd_A	2147483647	1901	0	0
prefix_10_rd_A	2147483647	1858	0	0
prefix_1_rd_A	2147483647	1810	0	0
prefix_2_rd_A	2147483647	1765	0	0
prefix_3_rd_A	2147483647	1868	0	0
prefix_4_rd_A	2147483647	1899	0	0
prefix_5_rd_A	2147483647	1835	0	0
prefix_6_rd_A	2147483647	1971	0	0
prefix_7_rd_A	2147483647	1801	0	0
prefix_8_rd_A	2147483647	1816	0	0
prefix_9_rd_A	2147483647	1876	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	745483	0	0
T57	660343	67779	0	0
T58	0	58628	0	0
T59	0	186406	0	0
T64	125430	0	0	0
T125	0	134985	0	0
T137	0	20073	0	0
T138	0	101932	0	0
T139	0	23503	0	0
T140	0	90657	0	0
T141	0	15967	0	0
T142	0	42437	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1737	0	0
T57	660343	107	0	0
T64	125430	0	0	0
T92	0	5	0	0
T94	0	26	0	0
T111	0	21	0	0
T113	0	59	0	0
T133	0	3	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	14	0	0
T162	0	13	0	0
T163	0	4	0	0
T164	0	87	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2695	0	0
T57	660343	64	0	0
T64	125430	0	0	0
T92	0	5	0	0
T94	0	63	0	0
T113	0	49	0	0
T133	0	5	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	2	0	0
T162	0	4	0	0
T163	0	15	0	0
T165	0	4	0	0
T166	0	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1901	0	0
T57	660343	60	0	0
T64	125430	0	0	0
T92	0	7	0	0
T94	0	28	0	0
T111	0	35	0	0
T113	0	50	0	0
T133	0	13	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	7	0	0
T162	0	11	0	0
T164	0	55	0	0
T167	0	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1858	0	0
T57	660343	95	0	0
T64	125430	0	0	0
T92	0	11	0	0
T94	0	14	0	0
T111	0	16	0	0
T113	0	32	0	0
T133	0	3	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	9	0	0
T162	0	34	0	0
T163	0	8	0	0
T167	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1810	0	0
T57	660343	94	0	0
T64	125430	0	0	0
T92	0	7	0	0
T94	0	23	0	0
T111	0	15	0	0
T113	0	20	0	0
T133	0	5	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	2	0	0
T162	0	27	0	0
T163	0	7	0	0
T167	0	10	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1765	0	0
T57	660343	57	0	0
T64	125430	0	0	0
T92	0	7	0	0
T94	0	22	0	0
T111	0	23	0	0
T113	0	27	0	0
T133	0	12	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T162	0	17	0	0
T163	0	5	0	0
T164	0	42	0	0
T167	0	28	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1868	0	0
T57	660343	79	0	0
T64	125430	0	0	0
T92	0	14	0	0
T94	0	19	0	0
T111	0	27	0	0
T113	0	26	0	0
T133	0	5	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	4	0	0
T162	0	13	0	0
T163	0	3	0	0
T167	0	16	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1899	0	0
T57	660343	62	0	0
T64	125430	0	0	0
T92	0	14	0	0
T94	0	20	0	0
T111	0	29	0	0
T113	0	21	0	0
T133	0	7	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	12	0	0
T162	0	16	0	0
T163	0	8	0	0
T167	0	24	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1835	0	0
T57	660343	119	0	0
T64	125430	0	0	0
T92	0	13	0	0
T94	0	33	0	0
T111	0	9	0	0
T113	0	20	0	0
T133	0	19	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T162	0	11	0	0
T163	0	2	0	0
T164	0	28	0	0
T167	0	18	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1971	0	0
T57	660343	87	0	0
T64	125430	0	0	0
T92	0	2	0	0
T94	0	46	0	0
T111	0	32	0	0
T113	0	32	0	0
T133	0	8	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	7	0	0
T162	0	21	0	0
T163	0	2	0	0
T167	0	21	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1801	0	0
T57	660343	79	0	0
T64	125430	0	0	0
T92	0	14	0	0
T94	0	23	0	0
T111	0	11	0	0
T113	0	25	0	0
T133	0	3	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	2	0	0
T162	0	15	0	0
T164	0	37	0	0
T167	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1816	0	0
T57	660343	79	0	0
T64	125430	0	0	0
T92	0	22	0	0
T94	0	25	0	0
T111	0	31	0	0
T113	0	31	0	0
T133	0	7	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	2	0	0
T162	0	13	0	0
T163	0	3	0	0
T167	0	33	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1876	0	0
T57	660343	103	0	0
T64	125430	0	0	0
T92	0	15	0	0
T94	0	34	0	0
T111	0	21	0	0
T113	0	35	0	0
T133	0	7	0	0
T143	515218	0	0	0
T144	241287	0	0	0
T145	170484	0	0	0
T146	31299	0	0	0
T147	422995	0	0	0
T148	69029	0	0	0
T149	963	0	0	0
T150	694094	0	0	0
T161	0	8	0	0
T162	0	9	0	0
T163	0	6	0	0
T167	0	12	0	0