Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	252339833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182244501

1

T1

73538

T2

1150

T3

816446

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	224287689	1			T1	81788		T2	773		T3	103762
values[0x0]	101051222	1			T1	19868		T2	538		T3	458430
values[0x1]	109245423	1			T1	21095		T2	584		T3	495558

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196085897	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

238498437

1

T1

85146

T2

1336

T3

107974

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1307957	1			T1	418		T3	7792		T7	3254
valid_sources[0x01]	2161921	1			T1	436		T3	7745		T7	3282
valid_sources[0x02]	1302984	1			T1	495		T3	7781		T7	3397
valid_sources[0x03]	2001736	1			T1	511		T3	7747		T7	3244
valid_sources[0x04]	1305952	1			T1	441		T3	7712		T7	3343
valid_sources[0x05]	1377681	1			T1	445		T3	7748		T7	3217
valid_sources[0x06]	1307283	1			T1	483		T3	7727		T7	3448
valid_sources[0x07]	1310030	1			T1	477		T3	7842		T7	3254
valid_sources[0x08]	1305909	1			T1	435		T3	7757		T7	3431
valid_sources[0x09]	1312718	1			T1	471		T3	7798		T7	3288
valid_sources[0x0a]	1958394	1			T1	442		T3	7672		T7	3348
valid_sources[0x0b]	1299668	1			T1	509		T3	7900		T7	3246
valid_sources[0x0c]	2184901	1			T1	464		T3	7713		T7	3264
valid_sources[0x0d]	1307032	1			T1	433		T3	7722		T7	3440
valid_sources[0x0e]	2116072	1			T1	422		T3	7820		T7	3279
valid_sources[0x0f]	1304559	1			T1	462		T3	7925		T7	3339
valid_sources[0x10]	3638808	1			T1	507		T3	7868		T7	3282
valid_sources[0x11]	1310110	1			T1	491		T3	7869		T7	3336
valid_sources[0x12]	3718173	1			T1	509		T3	7622		T7	3343
valid_sources[0x13]	1327586	1			T1	516		T3	7697		T7	3322
valid_sources[0x14]	2119498	1			T1	463		T3	7738		T7	3330
valid_sources[0x15]	1308310	1			T1	516		T3	7812		T7	3273
valid_sources[0x16]	2223119	1			T1	442		T3	7682		T7	3419
valid_sources[0x17]	1393868	1			T1	468		T3	7738		T7	3404
valid_sources[0x18]	1332540	1			T1	491		T3	7809		T7	3287
valid_sources[0x19]	1329697	1			T1	476		T3	7894		T7	3296
valid_sources[0x1a]	1314170	1			T1	394		T3	7897		T7	3245
valid_sources[0x1b]	1302884	1			T1	507		T3	7693		T7	3279
valid_sources[0x1c]	2334946	1			T1	490		T3	7910		T7	3323
valid_sources[0x1d]	1313676	1			T1	453		T3	7784		T7	3283
valid_sources[0x1e]	1308314	1			T1	501		T3	7762		T7	3287
valid_sources[0x1f]	1391917	1			T1	460		T3	7670		T7	3335
valid_sources[0x20]	1299865	1			T1	436		T3	7722		T7	3223
valid_sources[0x21]	1308000	1			T1	491		T3	7845		T7	3398
valid_sources[0x22]	3731610	1			T1	456		T3	7729		T7	3290
valid_sources[0x23]	1307685	1			T1	491		T3	7786		T7	3200
valid_sources[0x24]	1323199	1			T1	476		T3	7879		T7	3276
valid_sources[0x25]	1459314	1			T1	490		T3	7837		T7	3424
valid_sources[0x26]	2321466	1			T1	420		T3	7799		T7	3486
valid_sources[0x27]	1298860	1			T1	435		T3	7654		T7	3348
valid_sources[0x28]	2223034	1			T1	492		T3	7678		T7	3284
valid_sources[0x29]	1313243	1			T1	455		T3	7766		T7	3340
valid_sources[0x2a]	1316139	1			T1	505		T3	7948		T7	3350
valid_sources[0x2b]	2692233	1			T1	435		T3	7928		T7	3303
valid_sources[0x2c]	1314579	1			T1	494		T3	7789		T7	3177
valid_sources[0x2d]	1594912	1			T1	467		T3	7798		T7	3285
valid_sources[0x2e]	1329030	1			T1	538		T3	7847		T7	3252
valid_sources[0x2f]	1303429	1			T1	480		T3	7736		T7	3294
valid_sources[0x30]	1490062	1			T1	484		T3	7840		T7	3275
valid_sources[0x31]	1305951	1			T1	522		T3	7821		T7	3303
valid_sources[0x32]	2064293	1			T1	503		T3	7795		T7	3356
valid_sources[0x33]	2073490	1			T1	527		T2	1895		T3	7855
valid_sources[0x34]	1313667	1			T1	526		T3	7813		T7	3346
valid_sources[0x35]	1315085	1			T1	438		T3	7932		T7	3314
valid_sources[0x36]	1489052	1			T1	503		T3	7843		T7	3358
valid_sources[0x37]	1347990	1			T1	495		T3	7817		T7	3227
valid_sources[0x38]	2389049	1			T1	467		T3	7871		T7	3225
valid_sources[0x39]	1317146	1			T1	481		T3	7934		T7	3316
valid_sources[0x3a]	1312553	1			T1	479		T3	7898		T7	3372
valid_sources[0x3b]	3284739	1			T1	468		T3	7845		T7	3304
valid_sources[0x3c]	2178404	1			T1	473		T3	7734		T7	3297
valid_sources[0x3d]	1319705	1			T1	554		T3	7634		T7	3399
valid_sources[0x3e]	1313423	1			T1	445		T3	7749		T7	3341
valid_sources[0x3f]	1324721	1			T1	516		T3	7869		T7	3298
valid_sources[0x40]	1310529	1			T1	519		T3	7850		T7	3281
valid_sources[0x41]	4537644	1			T1	444		T3	7737		T7	3196
valid_sources[0x42]	1310566	1			T1	561		T3	7774		T7	3307
valid_sources[0x43]	1309987	1			T1	509		T3	7833		T7	3260
valid_sources[0x44]	3824559	1			T1	458		T3	7799		T7	3396
valid_sources[0x45]	3685281	1			T1	491		T3	7718		T7	3324
valid_sources[0x46]	1344170	1			T1	495		T3	7777		T7	3328
valid_sources[0x47]	2383864	1			T1	525		T3	7694		T7	3397
valid_sources[0x48]	1318376	1			T1	449		T3	7743		T7	3373
valid_sources[0x49]	1310437	1			T1	467		T3	7813		T7	3305
valid_sources[0x4a]	3463068	1			T1	466		T3	7834		T7	3298
valid_sources[0x4b]	1474339	1			T1	436		T3	7929		T7	3256
valid_sources[0x4c]	1313451	1			T1	413		T3	7722		T7	3292
valid_sources[0x4d]	1303428	1			T1	515		T3	7857		T7	3224
valid_sources[0x4e]	1419547	1			T1	505		T3	7745		T7	3178
valid_sources[0x4f]	3237766	1			T1	479		T3	7778		T7	3393
valid_sources[0x50]	1310598	1			T1	522		T3	7861		T7	3288
valid_sources[0x51]	1341907	1			T1	478		T3	7654		T7	3264
valid_sources[0x52]	1305227	1			T1	516		T3	7701		T7	3263
valid_sources[0x53]	1308925	1			T1	484		T3	7803		T7	3279
valid_sources[0x54]	2230449	1			T1	446		T3	7748		T7	3258
valid_sources[0x55]	1315853	1			T1	499		T3	7843		T7	3347
valid_sources[0x56]	1308626	1			T1	484		T3	7768		T7	3296
valid_sources[0x57]	1391450	1			T1	538		T3	7957		T7	3327
valid_sources[0x58]	2319333	1			T1	537		T3	7834		T7	3203
valid_sources[0x59]	1387562	1			T1	462		T3	7734		T7	3385
valid_sources[0x5a]	1312812	1			T1	471		T3	7775		T7	3193
valid_sources[0x5b]	1394983	1			T1	421		T3	7650		T7	3436
valid_sources[0x5c]	1311857	1			T1	470		T3	7839		T7	3333
valid_sources[0x5d]	1375688	1			T1	510		T3	7725		T7	3253
valid_sources[0x5e]	1319341	1			T1	484		T3	7716		T7	3290
valid_sources[0x5f]	1321961	1			T1	513		T3	7715		T7	3357
valid_sources[0x60]	1300470	1			T1	514		T3	7905		T7	3340
valid_sources[0x61]	2197769	1			T1	517		T3	7636		T7	3333
valid_sources[0x62]	1305898	1			T1	481		T3	7712		T7	3263
valid_sources[0x63]	1319643	1			T1	424		T3	7619		T7	3267
valid_sources[0x64]	1958761	1			T1	547		T3	7718		T7	3177
valid_sources[0x65]	1305980	1			T1	446		T3	7838		T7	3196
valid_sources[0x66]	1326425	1			T1	439		T3	7929		T7	3280
valid_sources[0x67]	1334673	1			T1	503		T3	7610		T7	3310
valid_sources[0x68]	1307010	1			T1	475		T3	7869		T7	3381
valid_sources[0x69]	1628884	1			T1	519		T3	7672		T7	3372
valid_sources[0x6a]	2166385	1			T1	434		T3	7862		T7	3268
valid_sources[0x6b]	1753639	1			T1	441		T3	7876		T7	3367
valid_sources[0x6c]	1322812	1			T1	503		T3	7884		T7	3236
valid_sources[0x6d]	1311914	1			T1	436		T3	7835		T7	3378
valid_sources[0x6e]	1311045	1			T1	539		T3	7732		T7	3362
valid_sources[0x6f]	1556665	1			T1	447		T3	7844		T7	3387
valid_sources[0x70]	1310212	1			T1	458		T3	8078		T7	3186
valid_sources[0x71]	1307654	1			T1	498		T3	7786		T7	3267
valid_sources[0x72]	1491417	1			T1	497		T3	7802		T7	3335
valid_sources[0x73]	1310237	1			T1	519		T3	7741		T7	3372
valid_sources[0x74]	1309287	1			T1	495		T3	7838		T7	3239
valid_sources[0x75]	1982212	1			T1	514		T3	7920		T7	3277
valid_sources[0x76]	1423056	1			T1	448		T3	7944		T7	3293
valid_sources[0x77]	1305463	1			T1	506		T3	7887		T7	3199
valid_sources[0x78]	1333263	1			T1	432		T3	7594		T7	3376
valid_sources[0x79]	1945792	1			T1	467		T3	7831		T7	3354
valid_sources[0x7a]	3642156	1			T1	466		T3	7858		T7	3310
valid_sources[0x7b]	1476416	1			T1	441		T3	7875		T7	3469
valid_sources[0x7c]	1307061	1			T1	509		T3	7822		T7	3269
valid_sources[0x7d]	2182335	1			T1	522		T3	7809		T7	3405
valid_sources[0x7e]	1417047	1			T1	465		T3	7609		T7	3313
valid_sources[0x7f]	1311547	1			T1	516		T3	7726		T7	3365
valid_sources[0x80]	2185382	1			T1	431		T3	7896		T7	3357

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70248666

1

T1

50164

T2

366

T3

323987

values[0x0]

all_enables

biggest_size

60106010

1

T1

12414

T2

395

T3

265565

values[0x1]

all_enables

biggest_size

51889825

1

T1

10960

T2

389

T3

226894