Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256330661

1

T1

49213

T2

745

T3

117517

full_word

182495031

1

T1

73538

T2

1150

T3

816446

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	438825412	1			T1	122751		T2	1895		T3	199161
auto[TlIntgErrCmd]	94	1			T121	4		T122	3		T123	8
auto[TlIntgErrData]	90	1			T121	4		T122	2		T123	5
auto[TlIntgErrBoth]	96	1			T121	2		T122	5		T123	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225061634

1

T1

81788

T2

773

T3

103762

auto[1]

213764058

1

T1

40963

T2

1122

T3

953988

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData] , auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	--	--	2

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154750292	1			T1	31624		T2	407		T3	713642
auto[TlIntgErrNone]	partial	auto[1]	101580104	1			T1	17589		T2	338		T3	461529
auto[TlIntgErrNone]	full_word	auto[0]	70311233	1			T1	50164		T2	366		T3	323987
auto[TlIntgErrNone]	full_word	auto[1]	112183783	1			T1	23374		T2	784		T3	492459
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T155	3		T146	2		T156	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T121	3		T122	1		T123	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T121	1		T122	1		T157	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T122	1		T123	1		T156	2
auto[TlIntgErrData]	partial	auto[0]	38	1			T121	2		T123	3		T155	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T121	2		T122	2		T123	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T146	1		T156	1		T157	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T121	2		T122	2		T123	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T122	3		T123	4		T155	8
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T158	2		T159	1		-	-