Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	913563	0	0
entropy_period_rd_A	2147483647	1954	0	0
intr_enable_rd_A	2147483647	2520	0	0
prefix_0_rd_A	2147483647	1623	0	0
prefix_10_rd_A	2147483647	1601	0	0
prefix_1_rd_A	2147483647	1825	0	0
prefix_2_rd_A	2147483647	1589	0	0
prefix_3_rd_A	2147483647	1724	0	0
prefix_4_rd_A	2147483647	1542	0	0
prefix_5_rd_A	2147483647	1691	0	0
prefix_6_rd_A	2147483647	1538	0	0
prefix_7_rd_A	2147483647	1704	0	0
prefix_8_rd_A	2147483647	1679	0	0
prefix_9_rd_A	2147483647	1788	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	913563	0	0
T16	940538	133694	0	0
T17	138201	0	0	0
T32	570723	0	0	0
T33	519272	0	0	0
T39	278727	0	0	0
T53	0	90467	0	0
T54	0	69093	0	0
T60	0	44963	0	0
T82	474868	0	0	0
T83	393057	0	0	0
T84	375554	0	0	0
T85	25042	0	0	0
T86	608281	0	0	0
T128	0	8410	0	0
T129	0	104587	0	0
T130	0	37230	0	0
T131	0	94572	0	0
T132	0	61454	0	0
T133	0	22480	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1954	0	0
T89	4176	7	0	0
T92	9339	64	0	0
T123	25082	113	0	0
T127	6021	31	0	0
T142	2718	1	0	0
T143	2157	1	0	0
T144	10028	25	0	0
T145	9656	22	0	0
T146	23976	136	0	0
T147	52428	410	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2520	0	0
T89	4176	21	0	0
T92	9339	42	0	0
T123	25082	199	0	0
T125	1542	5	0	0
T126	818	12	0	0
T143	2157	1	0	0
T144	10028	23	0	0
T145	9656	29	0	0
T148	2035	7	0	0
T149	915	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1623	0	0
T89	4176	26	0	0
T92	9339	25	0	0
T123	25082	84	0	0
T127	6021	22	0	0
T143	2157	9	0	0
T144	10028	51	0	0
T145	9656	25	0	0
T146	23976	84	0	0
T147	52428	386	0	0
T150	7902	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1601	0	0
T89	4176	15	0	0
T92	9339	36	0	0
T123	25082	72	0	0
T127	6021	12	0	0
T142	2718	1	0	0
T143	2157	4	0	0
T144	10028	8	0	0
T145	9656	21	0	0
T146	23976	58	0	0
T147	52428	387	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1825	0	0
T89	4176	20	0	0
T92	9339	11	0	0
T123	25082	92	0	0
T127	6021	21	0	0
T142	2718	9	0	0
T143	2157	4	0	0
T144	10028	48	0	0
T145	9656	44	0	0
T146	23976	90	0	0
T147	52428	462	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1589	0	0
T89	4176	17	0	0
T92	9339	23	0	0
T123	25082	73	0	0
T127	6021	24	0	0
T142	2718	9	0	0
T144	10028	60	0	0
T145	9656	26	0	0
T146	23976	70	0	0
T147	52428	389	0	0
T151	3252	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1724	0	0
T89	4176	18	0	0
T92	9339	6	0	0
T123	25082	89	0	0
T127	6021	27	0	0
T142	2718	2	0	0
T143	2157	1	0	0
T144	10028	13	0	0
T145	9656	10	0	0
T146	23976	90	0	0
T147	52428	395	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1542	0	0
T89	4176	13	0	0
T92	9339	28	0	0
T123	25082	69	0	0
T127	6021	15	0	0
T142	2718	1	0	0
T143	2157	4	0	0
T144	10028	37	0	0
T145	9656	15	0	0
T146	23976	83	0	0
T147	52428	407	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T89	4176	15	0	0
T92	9339	17	0	0
T123	25082	87	0	0
T127	6021	23	0	0
T142	2718	6	0	0
T144	10028	62	0	0
T145	9656	19	0	0
T146	23976	74	0	0
T147	52428	399	0	0
T150	7902	10	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T89	4176	16	0	0
T92	9339	23	0	0
T123	25082	71	0	0
T127	6021	14	0	0
T142	2718	2	0	0
T143	2157	5	0	0
T144	10028	29	0	0
T145	9656	24	0	0
T146	23976	76	0	0
T147	52428	390	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1704	0	0
T89	4176	18	0	0
T92	9339	26	0	0
T123	25082	86	0	0
T127	6021	26	0	0
T142	2718	1	0	0
T143	2157	6	0	0
T144	10028	3	0	0
T145	9656	9	0	0
T146	23976	72	0	0
T147	52428	457	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1679	0	0
T89	4176	11	0	0
T92	9339	19	0	0
T123	25082	91	0	0
T127	6021	31	0	0
T142	2718	2	0	0
T143	2157	3	0	0
T144	10028	56	0	0
T145	9656	28	0	0
T146	23976	92	0	0
T147	52428	432	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1788	0	0
T89	4176	19	0	0
T92	9339	15	0	0
T123	25082	74	0	0
T127	6021	27	0	0
T143	2157	6	0	0
T144	10028	19	0	0
T145	9656	49	0	0
T146	23976	67	0	0
T147	52428	412	0	0
T150	7902	15	0	0