Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256358456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183431775

1

T1

346787

T2

24509

T3

115817

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	227208419	1			T1	447283		T2	28715		T3	157921
values[0x0]	102125720	1			T1	215671		T2	6874		T3	31257
values[0x1]	110456092	1			T1	233045		T2	7503		T3	33451

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199194700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

240595531

1

T1

467044

T2

28963

T3

143254

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2680873	1			T1	3414		T2	257		T3	55
valid_sources[0x01]	1784600	1			T1	3561		T2	237		T3	54
valid_sources[0x02]	1323293	1			T1	3576		T2	90		T3	47
valid_sources[0x03]	1331569	1			T1	3504		T2	166		T3	59
valid_sources[0x04]	1326463	1			T1	3441		T2	163		T3	48
valid_sources[0x05]	1328703	1			T1	3528		T2	125		T3	46
valid_sources[0x06]	1542378	1			T1	3424		T2	180		T3	69
valid_sources[0x07]	1319967	1			T1	3450		T2	227		T3	63
valid_sources[0x08]	1368383	1			T1	3525		T2	124		T3	49
valid_sources[0x09]	1333801	1			T1	3575		T2	193		T3	60
valid_sources[0x0a]	1333128	1			T1	3560		T2	133		T3	54
valid_sources[0x0b]	1333077	1			T1	3563		T2	197		T3	54
valid_sources[0x0c]	1317229	1			T1	3625		T2	141		T3	62
valid_sources[0x0d]	1380952	1			T1	3473		T2	255		T3	51
valid_sources[0x0e]	1969044	1			T1	3451		T2	98		T3	66
valid_sources[0x0f]	1329655	1			T1	3490		T2	184		T3	54
valid_sources[0x10]	3271679	1			T1	3500		T2	207		T3	54
valid_sources[0x11]	1321826	1			T1	3590		T2	211		T3	63
valid_sources[0x12]	1327754	1			T1	3344		T2	124		T3	55
valid_sources[0x13]	1749655	1			T1	3498		T2	264		T3	59
valid_sources[0x14]	1467911	1			T1	3520		T2	96		T3	59
valid_sources[0x15]	1514850	1			T1	3533		T2	88		T3	60
valid_sources[0x16]	3751871	1			T1	3453		T2	162		T3	72
valid_sources[0x17]	1325679	1			T1	3483		T2	165		T3	49
valid_sources[0x18]	1330287	1			T1	3435		T2	285		T3	60
valid_sources[0x19]	1338253	1			T1	3340		T2	380		T3	62
valid_sources[0x1a]	1392076	1			T1	3528		T2	141		T3	70
valid_sources[0x1b]	1321718	1			T1	3242		T2	116		T3	48
valid_sources[0x1c]	1327246	1			T1	3459		T2	109		T3	51
valid_sources[0x1d]	1321436	1			T1	3476		T2	97		T3	71
valid_sources[0x1e]	1320978	1			T1	3389		T2	173		T3	54
valid_sources[0x1f]	2227466	1			T1	3604		T2	138		T3	49
valid_sources[0x20]	1312890	1			T1	3575		T2	178		T3	48
valid_sources[0x21]	1326622	1			T1	3465		T2	126		T3	51
valid_sources[0x22]	1324759	1			T1	3478		T2	215		T3	55
valid_sources[0x23]	1980478	1			T1	3383		T2	238		T3	62
valid_sources[0x24]	1326761	1			T1	3436		T2	153		T3	64
valid_sources[0x25]	1323892	1			T1	3544		T2	163		T3	66
valid_sources[0x26]	1328880	1			T1	3713		T2	279		T3	59
valid_sources[0x27]	1320389	1			T1	3324		T2	190		T3	59
valid_sources[0x28]	1323430	1			T1	3570		T2	156		T3	53
valid_sources[0x29]	1595638	1			T1	3598		T2	135		T3	60
valid_sources[0x2a]	1349421	1			T1	3458		T2	240		T3	52
valid_sources[0x2b]	1352382	1			T1	3439		T2	136		T3	66
valid_sources[0x2c]	1321085	1			T1	3339		T2	278		T3	61
valid_sources[0x2d]	1322508	1			T1	3513		T2	99		T3	64
valid_sources[0x2e]	1785843	1			T1	3408		T2	233		T3	47
valid_sources[0x2f]	1829561	1			T1	3560		T2	168		T3	57
valid_sources[0x30]	1332140	1			T1	3533		T2	90		T3	64
valid_sources[0x31]	1327650	1			T1	3497		T2	159		T3	54
valid_sources[0x32]	2087529	1			T1	3560		T2	131		T3	52
valid_sources[0x33]	1324001	1			T1	3532		T2	233		T3	59
valid_sources[0x34]	1325315	1			T1	3446		T2	262		T3	48
valid_sources[0x35]	1335206	1			T1	3458		T2	173		T3	52
valid_sources[0x36]	1324631	1			T1	3453		T2	76		T3	61
valid_sources[0x37]	1326161	1			T1	3481		T2	147		T3	54
valid_sources[0x38]	1327113	1			T1	3434		T2	86		T3	49
valid_sources[0x39]	1322330	1			T1	3504		T2	165		T3	56
valid_sources[0x3a]	2230861	1			T1	3353		T2	237		T3	44
valid_sources[0x3b]	1353319	1			T1	3382		T2	217		T3	48
valid_sources[0x3c]	1322303	1			T1	3477		T2	124		T3	50
valid_sources[0x3d]	1337814	1			T1	3423		T2	155		T3	47
valid_sources[0x3e]	6001354	1			T1	3482		T2	154		T3	49
valid_sources[0x3f]	1351210	1			T1	3561		T2	114		T3	44
valid_sources[0x40]	1321435	1			T1	3521		T2	162		T3	52
valid_sources[0x41]	1327293	1			T1	3408		T2	156		T3	57
valid_sources[0x42]	1406844	1			T1	3545		T2	138		T3	65
valid_sources[0x43]	1325177	1			T1	3497		T2	158		T3	56
valid_sources[0x44]	1499861	1			T1	3584		T2	124		T3	64
valid_sources[0x45]	4119999	1			T1	3561		T2	207		T3	48
valid_sources[0x46]	1317386	1			T1	3405		T2	155		T3	44
valid_sources[0x47]	1306164	1			T1	3606		T2	200		T3	45
valid_sources[0x48]	1352709	1			T1	3604		T2	94		T3	47
valid_sources[0x49]	2378099	1			T1	3530		T2	135		T3	46
valid_sources[0x4a]	3278649	1			T1	3569		T2	270		T3	49
valid_sources[0x4b]	1319427	1			T1	3524		T2	125		T3	52
valid_sources[0x4c]	1783401	1			T1	3561		T2	142		T3	45
valid_sources[0x4d]	1325924	1			T1	3490		T2	160		T3	60
valid_sources[0x4e]	1325692	1			T1	3541		T2	142		T3	51
valid_sources[0x4f]	1664126	1			T1	3679		T2	81		T3	50
valid_sources[0x50]	2898086	1			T1	3685		T2	255		T3	41
valid_sources[0x51]	1317568	1			T1	3575		T2	201		T3	55
valid_sources[0x52]	1325265	1			T1	3482		T2	135		T3	63
valid_sources[0x53]	1321156	1			T1	3569		T2	83		T3	55
valid_sources[0x54]	3751190	1			T1	3468		T2	156		T3	71
valid_sources[0x55]	1979460	1			T1	3494		T2	163		T3	58
valid_sources[0x56]	1790095	1			T1	3527		T2	203		T3	56
valid_sources[0x57]	1983308	1			T1	3421		T2	107		T3	60
valid_sources[0x58]	1323206	1			T1	3530		T2	193		T3	57
valid_sources[0x59]	2262890	1			T1	3700		T2	158		T3	54
valid_sources[0x5a]	1322977	1			T1	3436		T2	151		T3	53
valid_sources[0x5b]	1318171	1			T1	3469		T2	199		T3	52
valid_sources[0x5c]	1329083	1			T1	3435		T2	183		T3	56
valid_sources[0x5d]	1336275	1			T1	3481		T2	86		T3	59
valid_sources[0x5e]	1329827	1			T1	3532		T2	121		T3	53
valid_sources[0x5f]	2068525	1			T1	3532		T2	98		T3	60
valid_sources[0x60]	2020022	1			T1	3373		T2	247		T3	64
valid_sources[0x61]	1708286	1			T1	3576		T2	194		T3	42
valid_sources[0x62]	1988414	1			T1	3468		T2	138		T3	43
valid_sources[0x63]	3686770	1			T1	3428		T2	173		T3	46
valid_sources[0x64]	1321444	1			T1	3461		T2	136		T3	41
valid_sources[0x65]	1799265	1			T1	3566		T2	228		T3	59
valid_sources[0x66]	1340891	1			T1	3485		T2	102		T3	59
valid_sources[0x67]	1319163	1			T1	3490		T2	241		T3	59
valid_sources[0x68]	3276434	1			T1	3555		T2	88		T3	48
valid_sources[0x69]	1685929	1			T1	3507		T2	168		T3	62
valid_sources[0x6a]	2626566	1			T1	3630		T2	222		T3	60
valid_sources[0x6b]	1325616	1			T1	3420		T2	182		T3	60
valid_sources[0x6c]	2133173	1			T1	3452		T2	169		T3	53
valid_sources[0x6d]	2627682	1			T1	3650		T2	139		T3	58
valid_sources[0x6e]	1325509	1			T1	3517		T2	108		T3	51
valid_sources[0x6f]	1327247	1			T1	3610		T2	232		T3	49
valid_sources[0x70]	1320651	1			T1	3455		T2	101		T3	46
valid_sources[0x71]	1324519	1			T1	3441		T2	125		T3	55
valid_sources[0x72]	1539895	1			T1	3603		T2	216		T3	54
valid_sources[0x73]	1597646	1			T1	3567		T2	119		T3	60
valid_sources[0x74]	1323863	1			T1	3396		T2	163		T3	54
valid_sources[0x75]	1326384	1			T1	3477		T2	157		T3	51
valid_sources[0x76]	1322894	1			T1	3589		T2	173		T3	54
valid_sources[0x77]	1437448	1			T1	3562		T2	194		T3	52
valid_sources[0x78]	1327740	1			T1	3576		T2	186		T3	47
valid_sources[0x79]	1452268	1			T1	3503		T2	105		T3	49
valid_sources[0x7a]	1322301	1			T1	3471		T2	249		T3	50
valid_sources[0x7b]	1331104	1			T1	3399		T2	144		T3	62
valid_sources[0x7c]	1314281	1			T1	3469		T2	136		T3	59
valid_sources[0x7d]	1324066	1			T1	3427		T2	148		T3	75
valid_sources[0x7e]	1345940	1			T1	3513		T2	233		T3	46
valid_sources[0x7f]	1331254	1			T1	3602		T2	193		T3	69
valid_sources[0x80]	1327295	1			T1	3492		T2	121		T3	45

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70764137

1

T1

116563

T2

17033

T3

79541

values[0x0]

all_enables

biggest_size

60510000

1

T1

124637

T2

4046

T3

19355

values[0x1]

all_enables

biggest_size

52157638

1

T1

105587

T2

3430

T3

16921