Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259709018

1

T1

549212

T2

18583

T3

106812

full_word

183643376

1

T1

346787

T2

24509

T3

115817

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	443352094	1			T1	895999		T2	43092		T3	222629
auto[TlIntgErrCmd]	112	1			T124	5		T125	3		T126	3
auto[TlIntgErrData]	105	1			T124	3		T125	9		T126	8
auto[TlIntgErrBoth]	83	1			T124	2		T125	8		T126	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227859954

1

T1

447283

T2

28715

T3

157921

auto[1]

215492440

1

T1

448716

T2

14377

T3

64708

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157043019	1			T1	330720		T2	11682		T3	78380
auto[TlIntgErrNone]	partial	auto[1]	102665729	1			T1	218492		T2	6901		T3	28432
auto[TlIntgErrNone]	full_word	auto[0]	70816804	1			T1	116563		T2	17033		T3	79541
auto[TlIntgErrNone]	full_word	auto[1]	112826542	1			T1	230224		T2	7476		T3	36276
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T124	3		T125	2		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T124	2		T125	1		T126	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T164	1		T165	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T164	1		T149	1		T168	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T124	2		T125	4		T126	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T124	1		T125	5		T126	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T169	1		T170	1		T163	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T168	1		T171	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T125	5		T126	3		T168	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T124	2		T125	3		T126	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T165	1		T173	1		T174	2
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T126	1		T168	1		-	-