Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	770900	0	0
entropy_period_rd_A	2147483647	1694	0	0
intr_enable_rd_A	2147483647	2131	0	0
prefix_0_rd_A	2147483647	1361	0	0
prefix_10_rd_A	2147483647	1453	0	0
prefix_1_rd_A	2147483647	1331	0	0
prefix_2_rd_A	2147483647	1542	0	0
prefix_3_rd_A	2147483647	1578	0	0
prefix_4_rd_A	2147483647	1302	0	0
prefix_5_rd_A	2147483647	1423	0	0
prefix_6_rd_A	2147483647	1438	0	0
prefix_7_rd_A	2147483647	1439	0	0
prefix_8_rd_A	2147483647	1449	0	0
prefix_9_rd_A	2147483647	1552	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	770900	0	0
T10	802465	0	0	0
T17	91840	0	0	0
T18	89448	0	0	0
T38	137274	14359	0	0
T40	0	64674	0	0
T42	0	68130	0	0
T48	165226	0	0	0
T49	660999	0	0	0
T50	216462	0	0	0
T51	103538	0	0	0
T52	894	0	0	0
T53	20864	0	0	0
T130	0	31990	0	0
T131	0	5530	0	0
T132	0	29847	0	0
T133	0	86045	0	0
T134	0	68875	0	0
T135	0	91698	0	0
T136	0	8174	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1694	0	0
T91	2840	10	0	0
T94	5576	22	0	0
T95	7136	11	0	0
T96	3350	5	0	0
T124	12529	55	0	0
T148	10330	20	0	0
T149	11214	20	0	0
T150	3757	15	0	0
T151	4358	11	0	0
T152	5313	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2131	0	0
T91	2840	13	0	0
T94	5576	25	0	0
T95	7136	9	0	0
T96	3350	4	0	0
T124	12529	84	0	0
T148	10330	2	0	0
T149	11214	35	0	0
T150	3757	8	0	0
T153	1860	21	0	0
T154	1438	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1361	0	0
T91	2840	13	0	0
T94	5576	22	0	0
T96	3350	6	0	0
T124	12529	34	0	0
T148	10330	16	0	0
T149	11214	28	0	0
T150	3757	10	0	0
T151	4358	9	0	0
T152	5313	7	0	0
T153	1860	7	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1453	0	0
T91	2840	6	0	0
T94	5576	24	0	0
T95	7136	11	0	0
T96	3350	14	0	0
T124	12529	29	0	0
T148	10330	42	0	0
T149	11214	19	0	0
T150	3757	7	0	0
T151	4358	5	0	0
T153	1860	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1331	0	0
T91	2840	2	0	0
T94	5576	29	0	0
T95	7136	11	0	0
T96	3350	13	0	0
T124	12529	39	0	0
T148	10330	34	0	0
T149	11214	35	0	0
T150	3757	5	0	0
T151	4358	3	0	0
T153	1860	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1542	0	0
T91	2840	17	0	0
T94	5576	17	0	0
T95	7136	21	0	0
T96	3350	8	0	0
T124	12529	31	0	0
T148	10330	16	0	0
T149	11214	15	0	0
T150	3757	12	0	0
T151	4358	9	0	0
T153	1860	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1578	0	0
T91	2840	1	0	0
T94	5576	21	0	0
T95	7136	9	0	0
T96	3350	17	0	0
T124	12529	36	0	0
T148	10330	53	0	0
T149	11214	18	0	0
T150	3757	8	0	0
T151	4358	12	0	0
T153	1860	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1302	0	0
T91	2840	8	0	0
T94	5576	17	0	0
T95	7136	11	0	0
T96	3350	15	0	0
T124	12529	47	0	0
T148	10330	18	0	0
T149	11214	9	0	0
T150	3757	7	0	0
T151	4358	7	0	0
T153	1860	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1423	0	0
T91	2840	15	0	0
T94	5576	22	0	0
T95	7136	16	0	0
T96	3350	6	0	0
T124	12529	42	0	0
T148	10330	21	0	0
T149	11214	17	0	0
T150	3757	5	0	0
T151	4358	5	0	0
T153	1860	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1438	0	0
T91	2840	11	0	0
T94	5576	17	0	0
T95	7136	9	0	0
T96	3350	13	0	0
T124	12529	29	0	0
T148	10330	10	0	0
T149	11214	18	0	0
T150	3757	2	0	0
T151	4358	18	0	0
T153	1860	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1439	0	0
T91	2840	3	0	0
T94	5576	23	0	0
T95	7136	17	0	0
T96	3350	13	0	0
T124	12529	30	0	0
T148	10330	8	0	0
T149	11214	18	0	0
T151	4358	11	0	0
T152	5313	33	0	0
T153	1860	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449	0	0
T91	2840	9	0	0
T94	5576	10	0	0
T95	7136	16	0	0
T96	3350	15	0	0
T124	12529	52	0	0
T148	10330	30	0	0
T149	11214	5	0	0
T150	3757	8	0	0
T151	4358	5	0	0
T153	1860	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1552	0	0
T91	2840	8	0	0
T94	5576	17	0	0
T95	7136	6	0	0
T96	3350	10	0	0
T124	12529	42	0	0
T148	10330	21	0	0
T149	11214	21	0	0
T150	3757	8	0	0
T153	1860	3	0	0
T155	13712	7	0	0