Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
198174 |
1 |
|
|
T1 |
228 |
|
T8 |
82 |
|
T10 |
70 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
105785 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67256 |
1 |
|
|
T1 |
226 |
|
T8 |
81 |
|
T10 |
69 |
seven_bytes |
3558 |
1 |
|
|
T39 |
76 |
|
T41 |
1 |
|
T57 |
29 |
six_bytes |
3540 |
1 |
|
|
T39 |
66 |
|
T41 |
4 |
|
T57 |
22 |
five_bytes |
3553 |
1 |
|
|
T39 |
68 |
|
T41 |
3 |
|
T57 |
20 |
four_bytes |
3648 |
1 |
|
|
T39 |
65 |
|
T41 |
3 |
|
T57 |
20 |
three_bytes |
3586 |
1 |
|
|
T39 |
76 |
|
T41 |
5 |
|
T57 |
27 |
two_bytes |
3663 |
1 |
|
|
T39 |
63 |
|
T41 |
1 |
|
T57 |
21 |
one_byte |
3585 |
1 |
|
|
T39 |
65 |
|
T41 |
1 |
|
T57 |
25 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
194488 |
1 |
|
|
T1 |
224 |
|
T8 |
80 |
|
T10 |
68 |
auto[1] |
3686 |
1 |
|
|
T1 |
4 |
|
T8 |
2 |
|
T10 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
198174 |
1 |
|
|
T1 |
228 |
|
T8 |
82 |
|
T10 |
70 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
198165 |
1 |
|
|
T1 |
228 |
|
T8 |
82 |
|
T10 |
70 |
auto[1] |
9 |
1 |
|
|
T181 |
1 |
|
T182 |
1 |
|
T183 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1252 |
1 |
|
|
T1 |
2 |
|
T8 |
1 |
|
T10 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3686 |
1 |
|
|
T1 |
4 |
|
T8 |
2 |
|
T10 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186002 |
1 |
|
|
T10 |
47 |
|
T38 |
151 |
|
T39 |
1425 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
97070 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65834 |
1 |
|
|
T10 |
46 |
|
T38 |
149 |
|
T39 |
31 |
seven_bytes |
3299 |
1 |
|
|
T39 |
35 |
|
T41 |
1 |
|
T57 |
23 |
six_bytes |
3352 |
1 |
|
|
T39 |
41 |
|
T57 |
21 |
|
T19 |
74 |
five_bytes |
3264 |
1 |
|
|
T39 |
41 |
|
T41 |
2 |
|
T57 |
23 |
four_bytes |
3292 |
1 |
|
|
T39 |
24 |
|
T41 |
2 |
|
T57 |
15 |
three_bytes |
3315 |
1 |
|
|
T39 |
35 |
|
T41 |
1 |
|
T57 |
14 |
two_bytes |
3317 |
1 |
|
|
T39 |
31 |
|
T41 |
1 |
|
T57 |
28 |
one_byte |
3259 |
1 |
|
|
T39 |
45 |
|
T57 |
18 |
|
T19 |
71 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182486 |
1 |
|
|
T10 |
45 |
|
T38 |
147 |
|
T39 |
1407 |
auto[1] |
3516 |
1 |
|
|
T10 |
2 |
|
T38 |
4 |
|
T39 |
18 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186002 |
1 |
|
|
T10 |
47 |
|
T38 |
151 |
|
T39 |
1425 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
185992 |
1 |
|
|
T10 |
47 |
|
T38 |
151 |
|
T39 |
1425 |
auto[1] |
10 |
1 |
|
|
T120 |
1 |
|
T184 |
1 |
|
T185 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1225 |
1 |
|
|
T10 |
1 |
|
T38 |
2 |
|
T39 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3516 |
1 |
|
|
T10 |
2 |
|
T38 |
4 |
|
T39 |
18 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
361073 |
1 |
|
|
T1 |
94 |
|
T8 |
184 |
|
T10 |
221 |
auto[1] |
482 |
1 |
|
|
T48 |
62 |
|
T50 |
36 |
|
T51 |
46 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
193275 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
122866 |
1 |
|
|
T1 |
92 |
|
T8 |
181 |
|
T10 |
218 |
seven_bytes |
6509 |
1 |
|
|
T39 |
113 |
|
T41 |
8 |
|
T57 |
37 |
six_bytes |
6588 |
1 |
|
|
T39 |
127 |
|
T41 |
13 |
|
T57 |
64 |
five_bytes |
6541 |
1 |
|
|
T39 |
114 |
|
T41 |
10 |
|
T57 |
51 |
four_bytes |
6448 |
1 |
|
|
T39 |
114 |
|
T41 |
8 |
|
T57 |
52 |
three_bytes |
6444 |
1 |
|
|
T39 |
107 |
|
T41 |
13 |
|
T57 |
56 |
two_bytes |
6472 |
1 |
|
|
T39 |
105 |
|
T41 |
12 |
|
T57 |
47 |
one_byte |
6412 |
1 |
|
|
T39 |
127 |
|
T41 |
14 |
|
T57 |
46 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
354743 |
1 |
|
|
T1 |
90 |
|
T8 |
178 |
|
T10 |
215 |
auto[1] |
6812 |
1 |
|
|
T1 |
4 |
|
T8 |
6 |
|
T10 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
361555 |
1 |
|
|
T1 |
94 |
|
T8 |
184 |
|
T10 |
221 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
361538 |
1 |
|
|
T1 |
94 |
|
T8 |
184 |
|
T10 |
221 |
auto[1] |
17 |
1 |
|
|
T20 |
1 |
|
T186 |
1 |
|
T187 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2309 |
1 |
|
|
T1 |
2 |
|
T8 |
3 |
|
T10 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6812 |
1 |
|
|
T1 |
4 |
|
T8 |
6 |
|
T10 |
6 |