Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260410480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187043122

1

T1

84000

T2

19181

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	231905321	1			T1	94974		T2	12829		T3	1
values[0x0]	103545106	1			T1	24380		T2	5122		T3	7
values[0x1]	112003175	1			T1	25961		T2	5037		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202276764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

245176838

1

T1

98404

T2

20158

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4551260	1			T1	442		T2	66		T12	3049
valid_sources[0x01]	1980000	1			T1	647		T2	72		T12	3021
valid_sources[0x02]	1337144	1			T1	889		T2	75		T12	3421
valid_sources[0x03]	1325527	1			T1	445		T2	78		T12	3211
valid_sources[0x04]	1333351	1			T1	805		T2	110		T12	3090
valid_sources[0x05]	1329031	1			T1	626		T2	74		T12	3170
valid_sources[0x06]	1334478	1			T1	766		T2	83		T12	3178
valid_sources[0x07]	1322957	1			T1	425		T2	70		T12	3122
valid_sources[0x08]	2289244	1			T1	405		T2	87		T12	3056
valid_sources[0x09]	3975243	1			T1	474		T2	83		T12	3302
valid_sources[0x0a]	1376010	1			T1	550		T2	88		T12	3161
valid_sources[0x0b]	1319327	1			T1	557		T2	77		T12	3051
valid_sources[0x0c]	2196448	1			T1	539		T2	107		T12	3251
valid_sources[0x0d]	2184461	1			T1	663		T2	79		T12	3237
valid_sources[0x0e]	1984023	1			T1	467		T2	71		T12	3245
valid_sources[0x0f]	1318512	1			T1	585		T2	118		T12	3391
valid_sources[0x10]	3664302	1			T1	564		T2	72		T12	3199
valid_sources[0x11]	1323244	1			T1	880		T2	90		T12	3133
valid_sources[0x12]	1318730	1			T1	443		T2	81		T12	3163
valid_sources[0x13]	1320497	1			T1	657		T2	102		T12	3100
valid_sources[0x14]	1398790	1			T1	266		T2	106		T12	3074
valid_sources[0x15]	1901752	1			T1	434		T2	76		T12	2983
valid_sources[0x16]	1844889	1			T1	622		T2	88		T12	3161
valid_sources[0x17]	1325918	1			T1	560		T2	91		T12	3269
valid_sources[0x18]	1381431	1			T1	545		T2	112		T12	3584
valid_sources[0x19]	1330554	1			T1	264		T2	101		T12	3285
valid_sources[0x1a]	1637104	1			T1	717		T2	86		T12	3254
valid_sources[0x1b]	2245552	1			T1	488		T2	90		T12	3046
valid_sources[0x1c]	2056949	1			T1	621		T2	102		T12	3161
valid_sources[0x1d]	1331187	1			T1	454		T2	84		T12	3079
valid_sources[0x1e]	1386751	1			T1	713		T2	93		T12	3156
valid_sources[0x1f]	1985958	1			T1	561		T2	82		T12	3334
valid_sources[0x20]	1317081	1			T1	403		T2	90		T12	3345
valid_sources[0x21]	1327184	1			T1	348		T2	98		T12	3182
valid_sources[0x22]	1983817	1			T1	508		T2	95		T12	3083
valid_sources[0x23]	3756808	1			T1	577		T2	93		T12	2885
valid_sources[0x24]	3329946	1			T1	558		T2	84		T12	3325
valid_sources[0x25]	2212358	1			T1	563		T2	88		T12	3306
valid_sources[0x26]	1323659	1			T1	618		T2	85		T12	3181
valid_sources[0x27]	1324128	1			T1	729		T2	97		T12	3281
valid_sources[0x28]	2022883	1			T1	744		T2	107		T12	3114
valid_sources[0x29]	2173040	1			T1	466		T2	118		T12	3118
valid_sources[0x2a]	1334363	1			T1	796		T2	83		T12	3328
valid_sources[0x2b]	1839102	1			T1	331		T2	101		T12	3110
valid_sources[0x2c]	1323305	1			T1	454		T2	91		T12	3241
valid_sources[0x2d]	1328895	1			T1	700		T2	79		T12	3052
valid_sources[0x2e]	1326361	1			T1	595		T2	109		T12	3158
valid_sources[0x2f]	1325589	1			T1	596		T2	91		T12	2994
valid_sources[0x30]	1332462	1			T1	406		T2	79		T12	3181
valid_sources[0x31]	2223030	1			T1	631		T2	82		T12	3273
valid_sources[0x32]	1316768	1			T1	627		T2	92		T12	3199
valid_sources[0x33]	1387482	1			T1	808		T2	104		T12	3309
valid_sources[0x34]	1789930	1			T1	590		T2	86		T12	3177
valid_sources[0x35]	1320437	1			T1	644		T2	99		T12	3324
valid_sources[0x36]	1319854	1			T1	585		T2	107		T12	3037
valid_sources[0x37]	1323775	1			T1	689		T2	110		T12	3027
valid_sources[0x38]	1319305	1			T1	632		T2	87		T12	3157
valid_sources[0x39]	1328257	1			T1	676		T2	81		T12	3318
valid_sources[0x3a]	3323358	1			T1	654		T2	118		T12	3119
valid_sources[0x3b]	1328689	1			T1	606		T2	104		T12	3020
valid_sources[0x3c]	1333367	1			T1	424		T2	87		T12	3147
valid_sources[0x3d]	1407339	1			T1	507		T2	76		T12	3344
valid_sources[0x3e]	1328389	1			T1	533		T2	104		T12	3047
valid_sources[0x3f]	1326068	1			T1	451		T2	86		T12	3126
valid_sources[0x40]	1477589	1			T1	502		T2	90		T12	3347
valid_sources[0x41]	1335736	1			T1	342		T2	106		T12	3264
valid_sources[0x42]	1326863	1			T1	516		T2	77		T12	2963
valid_sources[0x43]	1331028	1			T1	723		T2	87		T12	3361
valid_sources[0x44]	1941123	1			T1	475		T2	72		T12	3342
valid_sources[0x45]	3387017	1			T1	579		T2	85		T12	3255
valid_sources[0x46]	2315954	1			T1	600		T2	81		T12	3228
valid_sources[0x47]	1321731	1			T1	804		T2	86		T12	3127
valid_sources[0x48]	1354830	1			T1	687		T2	74		T12	3030
valid_sources[0x49]	1325897	1			T1	731		T2	104		T12	3199
valid_sources[0x4a]	1326614	1			T1	663		T2	109		T12	3370
valid_sources[0x4b]	4111018	1			T1	463		T2	83		T12	3156
valid_sources[0x4c]	1379430	1			T1	588		T2	74		T12	3573
valid_sources[0x4d]	3334718	1			T1	494		T2	85		T12	3134
valid_sources[0x4e]	1771103	1			T1	179		T2	98		T12	3278
valid_sources[0x4f]	1444693	1			T1	583		T2	82		T12	3120
valid_sources[0x50]	2181460	1			T1	510		T2	78		T12	3421
valid_sources[0x51]	1324521	1			T1	422		T2	89		T12	3141
valid_sources[0x52]	1327545	1			T1	839		T2	106		T12	3058
valid_sources[0x53]	3629957	1			T1	673		T2	74		T12	3235
valid_sources[0x54]	1877287	1			T1	305		T2	121		T12	3184
valid_sources[0x55]	1781695	1			T1	443		T2	82		T12	3420
valid_sources[0x56]	1336149	1			T1	703		T2	90		T12	3116
valid_sources[0x57]	2164794	1			T1	363		T2	84		T12	3049
valid_sources[0x58]	1779460	1			T1	599		T2	76		T12	3365
valid_sources[0x59]	4337784	1			T1	606		T2	83		T12	3338
valid_sources[0x5a]	1413686	1			T1	559		T2	111		T12	3317
valid_sources[0x5b]	1334843	1			T1	609		T2	103		T12	3203
valid_sources[0x5c]	1498744	1			T1	439		T2	89		T12	3017
valid_sources[0x5d]	1337533	1			T1	843		T2	94		T12	3366
valid_sources[0x5e]	1327138	1			T1	728		T2	73		T12	3126
valid_sources[0x5f]	1326073	1			T1	548		T2	85		T12	3030
valid_sources[0x60]	1323013	1			T1	448		T2	81		T12	3182
valid_sources[0x61]	2164464	1			T1	779		T2	71		T12	3259
valid_sources[0x62]	1361380	1			T1	472		T2	102		T12	3128
valid_sources[0x63]	3385614	1			T1	482		T2	98		T12	3128
valid_sources[0x64]	1329138	1			T1	768		T2	106		T12	3410
valid_sources[0x65]	1328928	1			T1	559		T2	100		T12	3156
valid_sources[0x66]	2251503	1			T1	576		T2	105		T12	3313
valid_sources[0x67]	1353529	1			T1	621		T2	81		T12	3195
valid_sources[0x68]	1323319	1			T1	546		T2	91		T12	3237
valid_sources[0x69]	1323036	1			T1	544		T2	88		T12	2895
valid_sources[0x6a]	1325212	1			T1	562		T2	97		T12	3324
valid_sources[0x6b]	3316538	1			T1	713		T2	90		T12	3059
valid_sources[0x6c]	3296310	1			T1	448		T2	109		T12	3349
valid_sources[0x6d]	1315812	1			T1	389		T2	88		T12	3058
valid_sources[0x6e]	1495381	1			T1	840		T2	79		T12	3180
valid_sources[0x6f]	1321788	1			T1	554		T2	104		T12	3368
valid_sources[0x70]	1333134	1			T1	552		T2	87		T12	3433
valid_sources[0x71]	3692973	1			T1	659		T2	72		T12	2785
valid_sources[0x72]	1326146	1			T1	455		T2	101		T12	3350
valid_sources[0x73]	1319111	1			T1	661		T2	110		T12	2929
valid_sources[0x74]	1719110	1			T1	645		T2	98		T12	3311
valid_sources[0x75]	1447941	1			T1	562		T2	90		T12	3424
valid_sources[0x76]	1336503	1			T1	583		T2	93		T12	3096
valid_sources[0x77]	1356847	1			T1	382		T2	98		T12	3144
valid_sources[0x78]	3641581	1			T1	399		T2	81		T12	3357
valid_sources[0x79]	2191302	1			T1	528		T2	82		T12	3190
valid_sources[0x7a]	3269837	1			T1	567		T2	88		T12	3001
valid_sources[0x7b]	1318107	1			T1	372		T2	90		T12	3304
valid_sources[0x7c]	3407865	1			T1	545		T2	100		T12	3212
valid_sources[0x7d]	1326873	1			T1	670		T2	102		T12	3207
valid_sources[0x7e]	1320935	1			T1	586		T2	73		T12	2972
valid_sources[0x7f]	3297587	1			T1	508		T2	109		T12	3046
valid_sources[0x80]	1491445	1			T1	400		T2	65		T12	3237

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72564765

1

T1

55738

T2

10642

T3

1

values[0x0]

all_enables

biggest_size

61457595

1

T1

15045

T2

4341

T3

1

values[0x1]

all_enables

biggest_size

53020762

1

T1

13217

T2

4198

T3

1