Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

264117935

1

T1

61315

T2

3807

T3

12

full_word

187276234

1

T1

84000

T2

19181

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451393899	1			T1	145315		T2	22988		T3	15
auto[TlIntgErrCmd]	96	1			T123	3		T124	5		T193	2
auto[TlIntgErrData]	87	1			T122	8		T124	10		T193	3
auto[TlIntgErrBoth]	87	1			T122	2		T123	7		T124	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232619140

1

T1

94974

T2

12829

T3

1

auto[1]

218775029

1

T1

50341

T2

10159

T3

14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159996305	1			T1	39236		T2	2187		T7	241427
auto[TlIntgErrNone]	partial	auto[1]	104121384	1			T1	22079		T2	1620		T3	12
auto[TlIntgErrNone]	full_word	auto[0]	72622695	1			T1	55738		T2	10642		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	114653515	1			T1	28262		T2	8539		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T124	2		T189	2		T194	4
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T123	2		T124	2		T193	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T195	1		T196	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T123	1		T124	1		T189	2
auto[TlIntgErrData]	partial	auto[0]	46	1			T122	2		T124	6		T193	2
auto[TlIntgErrData]	partial	auto[1]	34	1			T122	6		T124	3		T193	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T124	1		T189	1		T194	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T192	1		T197	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T123	3		T124	3		T193	4
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T122	2		T123	3		T124	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T124	1		T190	1		T198	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T123	1		T190	1		T199	1