Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.48	98.75	96.74	100.00	92.31	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	343948	0	0
RunThenComplete_M	2147483647	3061577	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	343948	0	0
T1	108658	136	0	0
T2	305083	141	0	0
T3	1958	0	0	0
T7	148309	310	0	0
T8	483177	126	0	0
T9	386352	21	0	0
T10	595310	105	0	0
T12	187183	374	0	0
T13	149615	310	0	0
T14	3279	0	0	0
T35	0	246	0	0
T36	0	47	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3061577	0	0
T1	108658	763	0	0
T2	305083	359	0	0
T3	1958	0	0	0
T7	148309	5462	0	0
T8	483177	665	0	0
T9	386352	724	0	0
T10	595310	561	0	0
T12	187183	5526	0	0
T13	149615	5462	0	0
T14	3279	0	0	0
T35	0	5427	0	0
T36	0	1449	0	0