Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.48	98.75	96.74	100.00	92.31	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	857775	0	0
entropy_period_rd_A	2147483647	1618	0	0
intr_enable_rd_A	2147483647	2114	0	0
prefix_0_rd_A	2147483647	1614	0	0
prefix_10_rd_A	2147483647	1361	0	0
prefix_1_rd_A	2147483647	1606	0	0
prefix_2_rd_A	2147483647	1530	0	0
prefix_3_rd_A	2147483647	1481	0	0
prefix_4_rd_A	2147483647	1479	0	0
prefix_5_rd_A	2147483647	1521	0	0
prefix_6_rd_A	2147483647	1530	0	0
prefix_7_rd_A	2147483647	1438	0	0
prefix_8_rd_A	2147483647	1410	0	0
prefix_9_rd_A	2147483647	1506	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	857775	0	0
T23	600461	73718	0	0
T76	0	175911	0	0
T77	0	67280	0	0
T88	997878	0	0	0
T89	4175	0	0	0
T106	44106	0	0	0
T128	0	89021	0	0
T129	0	42157	0	0
T130	0	63349	0	0
T131	0	26137	0	0
T132	0	30063	0	0
T133	0	27317	0	0
T134	0	6603	0	0
T135	302972	0	0	0
T136	904157	0	0	0
T137	1042	0	0	0
T138	329281	0	0	0
T139	542415	0	0	0
T140	620571	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1618	0	0
T123	0	41	0	0
T150	479969	136	0	0
T151	0	32	0	0
T152	0	140	0	0
T153	0	20	0	0
T154	0	41	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	71	0	0
T158	0	49	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2114	0	0
T123	0	49	0	0
T125	0	22	0	0
T150	479969	80	0	0
T151	0	41	0	0
T152	0	298	0	0
T153	0	21	0	0
T154	0	16	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T168	0	22	0	0
T169	0	7	0	0
T170	0	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1614	0	0
T123	0	16	0	0
T150	479969	97	0	0
T151	0	22	0	0
T152	0	297	0	0
T153	0	11	0	0
T154	0	29	0	0
T156	0	2	0	0
T157	0	71	0	0
T158	0	43	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T171	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1361	0	0
T123	0	19	0	0
T150	479969	95	0	0
T151	0	24	0	0
T152	0	247	0	0
T153	0	15	0	0
T154	0	7	0	0
T155	0	2	0	0
T156	0	5	0	0
T157	0	70	0	0
T158	0	50	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606	0	0
T123	0	22	0	0
T150	479969	118	0	0
T151	0	34	0	0
T152	0	281	0	0
T153	0	17	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	68	0	0
T158	0	30	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1530	0	0
T123	0	23	0	0
T150	479969	100	0	0
T151	0	42	0	0
T152	0	299	0	0
T153	0	16	0	0
T154	0	23	0	0
T156	0	8	0	0
T157	0	61	0	0
T158	0	43	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T172	0	1	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1481	0	0
T123	0	14	0	0
T150	479969	68	0	0
T151	0	28	0	0
T152	0	239	0	0
T153	0	8	0	0
T154	0	26	0	0
T155	0	4	0	0
T156	0	3	0	0
T157	0	65	0	0
T158	0	45	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1479	0	0
T123	0	18	0	0
T150	479969	65	0	0
T151	0	20	0	0
T152	0	293	0	0
T153	0	19	0	0
T154	0	14	0	0
T155	0	4	0	0
T156	0	9	0	0
T157	0	72	0	0
T158	0	53	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1521	0	0
T123	0	16	0	0
T150	479969	135	0	0
T151	0	59	0	0
T152	0	230	0	0
T153	0	8	0	0
T154	0	3	0	0
T156	0	9	0	0
T157	0	56	0	0
T158	0	45	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T171	0	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1530	0	0
T123	0	44	0	0
T150	479969	113	0	0
T151	0	31	0	0
T152	0	304	0	0
T153	0	16	0	0
T154	0	10	0	0
T156	0	6	0	0
T157	0	48	0	0
T158	0	43	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T172	0	10	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1438	0	0
T123	0	14	0	0
T150	479969	144	0	0
T151	0	20	0	0
T152	0	244	0	0
T153	0	19	0	0
T154	0	13	0	0
T156	0	11	0	0
T157	0	50	0	0
T158	0	13	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T171	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1410	0	0
T123	0	14	0	0
T150	479969	91	0	0
T151	0	20	0	0
T152	0	264	0	0
T153	0	20	0	0
T156	0	4	0	0
T157	0	62	0	0
T158	0	38	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T171	0	10	0	0
T173	0	14	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1506	0	0
T123	0	28	0	0
T150	479969	107	0	0
T151	0	47	0	0
T152	0	252	0	0
T153	0	5	0	0
T154	0	5	0	0
T156	0	13	0	0
T157	0	78	0	0
T158	0	38	0	0
T159	543621	0	0	0
T160	831680	0	0	0
T161	3270	0	0	0
T162	225061	0	0	0
T163	3049	0	0	0
T164	2076	0	0	0
T165	218937	0	0	0
T166	135738	0	0	0
T167	102242	0	0	0
T172	0	3	0	0