Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168064 |
1 |
|
|
T3 |
69 |
|
T6 |
17 |
|
T12 |
274 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
89313 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57728 |
1 |
|
|
T3 |
68 |
|
T6 |
16 |
|
T12 |
267 |
seven_bytes |
3014 |
1 |
|
|
T9 |
65 |
|
T14 |
3 |
|
T24 |
24 |
six_bytes |
3095 |
1 |
|
|
T9 |
51 |
|
T14 |
6 |
|
T24 |
40 |
five_bytes |
3072 |
1 |
|
|
T9 |
64 |
|
T14 |
6 |
|
T24 |
41 |
four_bytes |
2944 |
1 |
|
|
T9 |
59 |
|
T14 |
8 |
|
T24 |
35 |
three_bytes |
3123 |
1 |
|
|
T9 |
60 |
|
T14 |
5 |
|
T24 |
36 |
two_bytes |
2845 |
1 |
|
|
T9 |
66 |
|
T14 |
4 |
|
T24 |
25 |
one_byte |
2930 |
1 |
|
|
T9 |
56 |
|
T14 |
7 |
|
T24 |
32 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164832 |
1 |
|
|
T3 |
67 |
|
T6 |
15 |
|
T12 |
260 |
auto[1] |
3232 |
1 |
|
|
T3 |
2 |
|
T6 |
2 |
|
T12 |
14 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168064 |
1 |
|
|
T3 |
69 |
|
T6 |
17 |
|
T12 |
274 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168052 |
1 |
|
|
T3 |
69 |
|
T6 |
17 |
|
T12 |
274 |
auto[1] |
12 |
1 |
|
|
T47 |
1 |
|
T20 |
1 |
|
T142 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1094 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T12 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3232 |
1 |
|
|
T3 |
2 |
|
T6 |
2 |
|
T12 |
14 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182132 |
1 |
|
|
T3 |
153 |
|
T6 |
57 |
|
T12 |
280 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
96852 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62137 |
1 |
|
|
T3 |
151 |
|
T6 |
56 |
|
T12 |
275 |
seven_bytes |
3403 |
1 |
|
|
T9 |
43 |
|
T14 |
6 |
|
T24 |
35 |
six_bytes |
3318 |
1 |
|
|
T9 |
42 |
|
T14 |
3 |
|
T24 |
41 |
five_bytes |
3251 |
1 |
|
|
T9 |
48 |
|
T14 |
5 |
|
T24 |
39 |
four_bytes |
3247 |
1 |
|
|
T9 |
39 |
|
T14 |
4 |
|
T24 |
33 |
three_bytes |
3329 |
1 |
|
|
T9 |
53 |
|
T14 |
13 |
|
T24 |
38 |
two_bytes |
3284 |
1 |
|
|
T9 |
56 |
|
T14 |
11 |
|
T24 |
29 |
one_byte |
3311 |
1 |
|
|
T9 |
46 |
|
T14 |
9 |
|
T24 |
44 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178654 |
1 |
|
|
T3 |
149 |
|
T6 |
55 |
|
T12 |
270 |
auto[1] |
3478 |
1 |
|
|
T3 |
4 |
|
T6 |
2 |
|
T12 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182132 |
1 |
|
|
T3 |
153 |
|
T6 |
57 |
|
T12 |
280 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182122 |
1 |
|
|
T3 |
153 |
|
T6 |
57 |
|
T12 |
280 |
auto[1] |
10 |
1 |
|
|
T19 |
1 |
|
T143 |
1 |
|
T144 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1173 |
1 |
|
|
T3 |
2 |
|
T6 |
1 |
|
T12 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3478 |
1 |
|
|
T3 |
4 |
|
T6 |
2 |
|
T12 |
10 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359340 |
1 |
|
|
T3 |
524 |
|
T6 |
16 |
|
T12 |
1230 |
auto[1] |
522 |
1 |
|
|
T19 |
19 |
|
T20 |
99 |
|
T21 |
38 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
190251 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
124146 |
1 |
|
|
T3 |
516 |
|
T6 |
15 |
|
T12 |
1212 |
seven_bytes |
6537 |
1 |
|
|
T9 |
77 |
|
T14 |
13 |
|
T24 |
70 |
six_bytes |
6300 |
1 |
|
|
T9 |
80 |
|
T14 |
18 |
|
T24 |
58 |
five_bytes |
6516 |
1 |
|
|
T9 |
86 |
|
T14 |
16 |
|
T24 |
64 |
four_bytes |
6452 |
1 |
|
|
T9 |
90 |
|
T14 |
9 |
|
T24 |
57 |
three_bytes |
6548 |
1 |
|
|
T9 |
106 |
|
T14 |
15 |
|
T24 |
58 |
two_bytes |
6456 |
1 |
|
|
T9 |
83 |
|
T14 |
16 |
|
T24 |
54 |
one_byte |
6656 |
1 |
|
|
T9 |
91 |
|
T14 |
16 |
|
T24 |
89 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
353100 |
1 |
|
|
T3 |
508 |
|
T6 |
14 |
|
T12 |
1194 |
auto[1] |
6762 |
1 |
|
|
T3 |
16 |
|
T6 |
2 |
|
T12 |
36 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359862 |
1 |
|
|
T3 |
524 |
|
T6 |
16 |
|
T12 |
1230 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359837 |
1 |
|
|
T3 |
524 |
|
T6 |
16 |
|
T12 |
1230 |
auto[1] |
25 |
1 |
|
|
T10 |
1 |
|
T24 |
1 |
|
T20 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2325 |
1 |
|
|
T3 |
8 |
|
T6 |
1 |
|
T12 |
18 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6762 |
1 |
|
|
T3 |
16 |
|
T6 |
2 |
|
T12 |
36 |