Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 260078186 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 187092960 1 T1 319183 T2 20554 T3 9723



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 231500360 1 T1 95540 T2 10531 T3 12195
values[0x0] 103663364 1 T1 131020 T2 5839 T3 2624
values[0x1] 112007422 1 T1 131166 T2 6126 T3 2754



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 202070105 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 245101041 1 T1 329225 T2 21293 T3 11733



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1365869 1 T1 1323 T2 110 T3 3
valid_sources[0x01] 1359747 1 T1 1369 T2 105 T3 5
valid_sources[0x02] 1479530 1 T1 1503 T2 82 T3 2
valid_sources[0x03] 1369131 1 T1 1195 T2 101 T3 6
valid_sources[0x04] 1373758 1 T1 1462 T2 77 T3 1
valid_sources[0x05] 3130466 1 T1 1502 T2 62 T3 4
valid_sources[0x06] 2215612 1 T1 1369 T2 79 T3 1
valid_sources[0x07] 1368437 1 T1 1537 T2 99 T6 39
valid_sources[0x08] 1456529 1 T1 1428 T2 110 T3 4
valid_sources[0x09] 2542554 1 T1 1486 T2 91 T3 2
valid_sources[0x0a] 1367597 1 T1 1405 T2 103 T3 1
valid_sources[0x0b] 1380020 1 T1 1606 T2 71 T6 45
valid_sources[0x0c] 1366416 1 T1 1448 T2 81 T3 1
valid_sources[0x0d] 1813717 1 T1 1436 T2 91 T3 2
valid_sources[0x0e] 1421643 1 T1 1320 T2 90 T6 45
valid_sources[0x0f] 1365240 1 T1 1380 T2 103 T3 4
valid_sources[0x10] 1370331 1 T1 1444 T2 96 T3 3
valid_sources[0x11] 2078177 1 T1 1422 T2 92 T3 2
valid_sources[0x12] 2280392 1 T1 1419 T2 84 T3 1
valid_sources[0x13] 1398366 1 T1 1290 T2 85 T3 1
valid_sources[0x14] 1368209 1 T1 1462 T2 75 T3 4
valid_sources[0x15] 2011284 1 T1 1375 T2 88 T3 3
valid_sources[0x16] 1362419 1 T1 1428 T2 80 T3 3
valid_sources[0x17] 1369178 1 T1 1582 T2 84 T3 4
valid_sources[0x18] 3956297 1 T1 1242 T2 90 T3 2
valid_sources[0x19] 1372844 1 T1 1523 T2 99 T3 4
valid_sources[0x1a] 2035896 1 T1 1415 T2 91 T3 1
valid_sources[0x1b] 1362334 1 T1 1408 T2 108 T3 4
valid_sources[0x1c] 1359760 1 T1 1365 T2 94 T3 3
valid_sources[0x1d] 1377705 1 T1 1205 T2 93 T3 5
valid_sources[0x1e] 1483351 1 T1 1407 T2 84 T3 2
valid_sources[0x1f] 1373652 1 T1 1561 T2 88 T3 3
valid_sources[0x20] 1360778 1 T1 1341 T2 109 T3 2
valid_sources[0x21] 1364699 1 T1 1380 T2 65 T3 3
valid_sources[0x22] 1370237 1 T1 1473 T2 94 T3 5
valid_sources[0x23] 1366971 1 T1 1469 T2 99 T3 5
valid_sources[0x24] 2208569 1 T1 1269 T2 100 T3 5
valid_sources[0x25] 2284591 1 T1 1389 T2 88 T3 1
valid_sources[0x26] 1665111 1 T1 1491 T2 97 T3 2
valid_sources[0x27] 3032934 1 T1 1375 T2 81 T3 2
valid_sources[0x28] 1368527 1 T1 1716 T2 79 T3 2
valid_sources[0x29] 1371206 1 T1 1327 T2 66 T6 48
valid_sources[0x2a] 1373534 1 T1 1445 T2 77 T3 3
valid_sources[0x2b] 1372979 1 T1 1233 T2 95 T3 1
valid_sources[0x2c] 1368858 1 T1 1329 T2 82 T3 3
valid_sources[0x2d] 1369905 1 T1 1330 T2 95 T3 1
valid_sources[0x2e] 2213472 1 T1 1350 T2 72 T3 2
valid_sources[0x2f] 1358256 1 T1 1320 T2 91 T3 7
valid_sources[0x30] 1821680 1 T1 1491 T2 90 T3 2
valid_sources[0x31] 1375456 1 T1 1372 T2 75 T3 4
valid_sources[0x32] 1373364 1 T1 1402 T2 92 T3 3
valid_sources[0x33] 1502244 1 T1 1413 T2 81 T3 3
valid_sources[0x34] 3360986 1 T1 1494 T2 101 T3 2
valid_sources[0x35] 3731286 1 T1 1329 T2 116 T3 1
valid_sources[0x36] 3345448 1 T1 1272 T2 63 T3 2
valid_sources[0x37] 2008467 1 T1 1273 T2 84 T3 2
valid_sources[0x38] 1372180 1 T1 1456 T2 77 T3 1
valid_sources[0x39] 1366443 1 T1 1401 T2 81 T6 39
valid_sources[0x3a] 1363849 1 T1 1506 T2 116 T3 1
valid_sources[0x3b] 1367398 1 T1 1466 T2 95 T3 4
valid_sources[0x3c] 1357141 1 T1 1280 T2 105 T3 1
valid_sources[0x3d] 1370280 1 T1 1453 T2 74 T3 2
valid_sources[0x3e] 1769269 1 T1 1267 T2 86 T3 2
valid_sources[0x3f] 2215450 1 T1 1418 T2 81 T3 5
valid_sources[0x40] 1366609 1 T1 1378 T2 90 T3 3
valid_sources[0x41] 1364289 1 T1 1240 T2 94 T3 3
valid_sources[0x42] 1367575 1 T1 1509 T2 84 T3 4
valid_sources[0x43] 1479920 1 T1 1527 T2 71 T3 5
valid_sources[0x44] 1388318 1 T1 1295 T2 100 T3 1
valid_sources[0x45] 1366370 1 T1 1250 T2 80 T3 1
valid_sources[0x46] 1369444 1 T1 1366 T2 104 T3 2
valid_sources[0x47] 1362700 1 T1 1354 T2 76 T3 7
valid_sources[0x48] 2233312 1 T1 1458 T2 100 T3 2
valid_sources[0x49] 1367921 1 T1 1435 T2 87 T3 1
valid_sources[0x4a] 1370366 1 T1 1562 T2 74 T3 6
valid_sources[0x4b] 1441581 1 T1 1385 T2 75 T6 48
valid_sources[0x4c] 1372598 1 T1 1520 T2 80 T3 2
valid_sources[0x4d] 3416337 1 T1 1480 T2 73 T3 6
valid_sources[0x4e] 3735783 1 T1 1411 T2 68 T3 3
valid_sources[0x4f] 2413439 1 T1 1494 T2 93 T3 2
valid_sources[0x50] 3337427 1 T1 1321 T2 86 T3 6
valid_sources[0x51] 1364947 1 T1 1324 T2 86 T3 1
valid_sources[0x52] 3317523 1 T1 1458 T2 75 T3 3
valid_sources[0x53] 2674453 1 T1 1290 T2 89 T3 3
valid_sources[0x54] 1513142 1 T1 1236 T2 95 T3 2
valid_sources[0x55] 1368816 1 T1 1312 T2 82 T3 3
valid_sources[0x56] 2313156 1 T1 1295 T2 80 T3 4
valid_sources[0x57] 1373035 1 T1 1503 T2 98 T3 1
valid_sources[0x58] 1358487 1 T1 1422 T2 93 T3 2
valid_sources[0x59] 1362638 1 T1 1511 T2 85 T6 45
valid_sources[0x5a] 1360247 1 T1 1261 T2 82 T3 2
valid_sources[0x5b] 1365778 1 T1 1372 T2 101 T3 4
valid_sources[0x5c] 1373903 1 T1 1257 T2 91 T3 4
valid_sources[0x5d] 1370595 1 T1 1367 T2 83 T3 4
valid_sources[0x5e] 1369533 1 T1 1453 T2 102 T3 2
valid_sources[0x5f] 2041867 1 T1 1434 T2 76 T3 1
valid_sources[0x60] 2027224 1 T1 1527 T2 89 T3 2
valid_sources[0x61] 1362390 1 T1 1424 T2 87 T3 2
valid_sources[0x62] 2304582 1 T1 1221 T2 65 T6 38
valid_sources[0x63] 3115386 1 T1 1402 T2 93 T3 2
valid_sources[0x64] 1366256 1 T1 1344 T2 75 T3 2
valid_sources[0x65] 1367914 1 T1 1459 T2 77 T3 2
valid_sources[0x66] 2562284 1 T1 1275 T2 77 T6 42
valid_sources[0x67] 1871043 1 T1 1534 T2 71 T3 2
valid_sources[0x68] 2279045 1 T1 1296 T2 83 T3 3
valid_sources[0x69] 2260314 1 T1 1304 T2 85 T3 7
valid_sources[0x6a] 1368304 1 T1 1247 T2 89 T3 2
valid_sources[0x6b] 1366880 1 T1 1584 T2 95 T3 3
valid_sources[0x6c] 1381327 1 T1 1431 T2 81 T3 3
valid_sources[0x6d] 1358471 1 T1 1274 T2 88 T3 3
valid_sources[0x6e] 3344112 1 T1 1454 T2 95 T3 4
valid_sources[0x6f] 4611357 1 T1 1383 T2 82 T3 2
valid_sources[0x70] 1374881 1 T1 1325 T2 82 T3 2
valid_sources[0x71] 2261597 1 T1 1424 T2 98 T3 5
valid_sources[0x72] 1369090 1 T1 1550 T2 80 T3 1
valid_sources[0x73] 1364859 1 T1 1260 T2 91 T3 4
valid_sources[0x74] 1369454 1 T1 1304 T2 80 T3 3
valid_sources[0x75] 1372583 1 T1 1228 T2 57 T3 6
valid_sources[0x76] 2423293 1 T1 1274 T2 86 T3 5
valid_sources[0x77] 1360825 1 T1 1364 T2 81 T3 1
valid_sources[0x78] 1369596 1 T1 1564 T2 72 T3 5
valid_sources[0x79] 1369555 1 T1 1167 T2 102 T3 8
valid_sources[0x7a] 3377239 1 T1 1428 T2 78 T3 8
valid_sources[0x7b] 1376209 1 T1 1374 T2 76 T3 5
valid_sources[0x7c] 2217128 1 T1 1406 T2 82 T6 38
valid_sources[0x7d] 1364382 1 T1 1163 T2 97 T3 2
valid_sources[0x7e] 1377774 1 T1 1328 T2 103 T6 50
valid_sources[0x7f] 1368686 1 T1 1323 T2 85 T3 1
valid_sources[0x80] 1364525 1 T1 1396 T2 112 T3 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 72089548 1 T1 60551 T2 10359 T3 6378
values[0x0] all_enables biggest_size 61719652 1 T1 129466 T2 5117 T3 1776
values[0x1] all_enables biggest_size 53283760 1 T1 129166 T2 5078 T3 1569

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%