Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263347556

1

T1

38543

T2

1942

T3

7850

full_word

187298290

1

T1

319183

T2

20554

T3

9723

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450645556	1			T1	357726		T2	22496		T3	17573
auto[TlIntgErrCmd]	95	1			T107	4		T108	1		T109	6
auto[TlIntgErrData]	90	1			T107	8		T108	5		T109	8
auto[TlIntgErrBoth]	105	1			T107	8		T108	4		T109	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232130029

1

T1

95540

T2

10531

T3

12195

auto[1]

218515817

1

T1

262186

T2

11965

T3

5378

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159988957	1			T1	34989		T2	172		T3	5817
auto[TlIntgErrNone]	partial	auto[1]	103358327	1			T1	3554		T2	1770		T3	2033
auto[TlIntgErrNone]	full_word	auto[0]	72140933	1			T1	60551		T2	10359		T3	6378
auto[TlIntgErrNone]	full_word	auto[1]	115157339	1			T1	258632		T2	10195		T3	3345
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T109	3		T150	3		T145	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T107	3		T108	1		T109	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T146	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T107	1		T150	1		T151	2
auto[TlIntgErrData]	partial	auto[0]	49	1			T107	4		T108	3		T109	3
auto[TlIntgErrData]	partial	auto[1]	34	1			T107	3		T108	2		T109	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T107	1		T109	1		T145	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T152	1		T153	1		T154	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T107	5		T109	4		T150	3
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T107	3		T108	3		T109	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T108	1		T154	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T150	1		T147	1		T148	1