Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	754884	0	0
entropy_period_rd_A	2147483647	2489	0	0
intr_enable_rd_A	2147483647	3645	0	0
prefix_0_rd_A	2147483647	2628	0	0
prefix_10_rd_A	2147483647	2612	0	0
prefix_1_rd_A	2147483647	2696	0	0
prefix_2_rd_A	2147483647	2530	0	0
prefix_3_rd_A	2147483647	2649	0	0
prefix_4_rd_A	2147483647	2610	0	0
prefix_5_rd_A	2147483647	2752	0	0
prefix_6_rd_A	2147483647	2638	0	0
prefix_7_rd_A	2147483647	2651	0	0
prefix_8_rd_A	2147483647	2696	0	0
prefix_9_rd_A	2147483647	2716	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	754884	0	0
T10	290776	0	0	0
T14	552563	48508	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	3325	0	0
T58	0	51826	0	0
T113	0	35999	0	0
T114	0	5529	0	0
T115	0	86609	0	0
T116	0	51531	0	0
T117	0	26364	0	0
T118	0	16434	0	0
T119	0	42238	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2489	0	0
T10	290776	0	0	0
T14	552563	161	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	45	0	0
T80	0	23	0	0
T82	0	24	0	0
T108	0	36	0	0
T114	0	25	0	0
T118	0	39	0	0
T128	0	98	0	0
T129	0	21	0	0
T130	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3645	0	0
T10	290776	0	0	0
T14	552563	103	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	30	0	0
T82	0	36	0	0
T108	0	111	0	0
T110	0	11	0	0
T114	0	17	0	0
T118	0	29	0	0
T128	0	74	0	0
T129	0	37	0	0
T130	0	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2628	0	0
T10	290776	0	0	0
T14	552563	138	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	17	0	0
T80	0	14	0	0
T82	0	23	0	0
T108	0	33	0	0
T114	0	41	0	0
T118	0	24	0	0
T128	0	105	0	0
T129	0	32	0	0
T130	0	18	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2612	0	0
T10	290776	0	0	0
T14	552563	174	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	29	0	0
T80	0	18	0	0
T82	0	28	0	0
T108	0	37	0	0
T114	0	29	0	0
T118	0	7	0	0
T128	0	97	0	0
T129	0	27	0	0
T130	0	19	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2696	0	0
T10	290776	0	0	0
T14	552563	180	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	17	0	0
T80	0	20	0	0
T82	0	32	0	0
T108	0	41	0	0
T114	0	34	0	0
T118	0	20	0	0
T128	0	98	0	0
T129	0	36	0	0
T130	0	19	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2530	0	0
T10	290776	0	0	0
T14	552563	149	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	28	0	0
T80	0	6	0	0
T82	0	21	0	0
T108	0	31	0	0
T114	0	36	0	0
T118	0	10	0	0
T128	0	81	0	0
T129	0	44	0	0
T130	0	19	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2649	0	0
T10	290776	0	0	0
T14	552563	156	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	27	0	0
T80	0	25	0	0
T82	0	14	0	0
T108	0	50	0	0
T114	0	32	0	0
T118	0	39	0	0
T128	0	111	0	0
T129	0	39	0	0
T130	0	21	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2610	0	0
T10	290776	0	0	0
T14	552563	128	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	15	0	0
T80	0	26	0	0
T82	0	24	0	0
T108	0	40	0	0
T114	0	26	0	0
T118	0	45	0	0
T128	0	43	0	0
T129	0	49	0	0
T130	0	26	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2752	0	0
T10	290776	0	0	0
T14	552563	115	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
T53	1280	0	0	0
T54	21102	0	0	0
T55	101964	0	0	0
T56	208011	0	0	0
T57	0	25	0	0
T80	0	18	0	0
T82	0	17	0	0
T108	0	27	0	0
T114	0	48	0	0
T118	0	35	0	0
T128	0	78	0	0
T129	0	41	0	0
T130	0	18	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2638	0	0
T10	290776	0	0	0
T14	552563	106	0	0
T15	1564	0	0	0
T24	413201	0	0	0
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T57	0	37	0	0
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T108	0	45	0	0
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T118	0	31	0	0
T128	0	88	0	0
T129	0	28	0	0
T130	0	21	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2651	0	0
T10	290776	0	0	0
T14	552563	168	0	0
T15	1564	0	0	0
T24	413201	0	0	0
T32	24603	0	0	0
T52	1105	0	0	0
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T55	101964	0	0	0
T56	208011	0	0	0
T57	0	32	0	0
T80	0	21	0	0
T82	0	17	0	0
T108	0	36	0	0
T114	0	27	0	0
T118	0	12	0	0
T128	0	109	0	0
T129	0	65	0	0
T130	0	11	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2696	0	0
T10	290776	0	0	0
T14	552563	97	0	0
T15	1564	0	0	0
T24	413201	0	0	0
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T128	0	83	0	0
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T130	0	19	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2716	0	0
T10	290776	0	0	0
T14	552563	156	0	0
T15	1564	0	0	0
T24	413201	0	0	0
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