Unified Coverage Report :: Module :: prim_trivium

Module : prim_trivium

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.62	100.00	88.37			94.12	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_entropy.u_entropy.u_prim_trivium	95.62	100.00	88.37			94.12	100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy.u_prim_trivium

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.62	100.00	88.37			94.12	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.62	100.00	88.37			94.12	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.57	100.00	87.83		100.00	100.00	100.00	gen_entropy.u_entropy

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_trivium

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
ALWAYS	139	4	4	100.00
ALWAYS	170	4	4	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	194	3	3	100.00
CONT_ASSIGN	202	1	1	100.00
ALWAYS	204	3	3	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	300	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' or '../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
119	1	1
120	1	1
121	1	1
122	1	1
139	1	1
140	1	1
141	1	1
142	1	1
170	1	1
172	1	1
173	1	1
175	1	1
188	1	1
189	1	1
194	1	1
195	1	1
197	1	1
202	1	1
204	1	1
205	1	1
207	1	1
210	1	1
284	1	1
285	1	1
288	1	1
289	1	1
291	1	1
296	1	1
300		unreachable

---

Cond Coverage for Module : prim_trivium

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       119
 EXPRESSION (en_i | update_init)
             --1-   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T6

 LINE       120
 EXPRESSION (seed_req_o & seed_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       170
 EXPRESSION (((!update)) ? state_q : state_update)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       188
 EXPRESSION (lockup & ((StrictLockupProtection | (~allow_lockup_i))))
             ---1--   -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Not Covered

 LINE       189
 EXPRESSION (restore ? StateSeed : (wr_en_seed ? state_seed : (update ? state_update : state_q)))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       189
 SUB-EXPRESSION (wr_en_seed ? state_seed : (update ? state_update : state_q))
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       189
 SUB-EXPRESSION (update ? state_update : state_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       202
 EXPRESSION ((seed_en_i | seed_req_q) & (((~seed_ack_i)) | ((~last_state_part))))
             ------------1-----------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       202
 SUB-EXPRESSION (seed_en_i | seed_req_q)
                 ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       202
 SUB-EXPRESSION (((~seed_ack_i)) | ((~last_state_part)))
                 -------1-------   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       210
 EXPRESSION (seed_en_i | seed_req_q)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6

 LINE       284
 EXPRESSION (state_idx_q == LastStatePart[(StateIdxWidth - 1):0])
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       285
 EXPRESSION ((wr_en_seed & last_state_part) ? '0 : ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q))
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       285
 SUB-EXPRESSION (wr_en_seed & last_state_part)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       285
 SUB-EXPRESSION ((wr_en_seed & ((~last_state_part))) ? ((state_idx_q + 1'b1)) : state_idx_q)
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       285
 SUB-EXPRESSION (wr_en_seed & ((~last_state_part)))
                 -----1----   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       296
 EXPRESSION (seed_req_o & seed_ack_i & last_state_part)
             -----1----   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T1,T3,T6

---

Branch Coverage for Module : prim_trivium

	Line No.	Total	Covered	Percent
Branches		17	16	94.12
TERNARY	189	4	3	75.00
TERNARY	285	3	3	100.00
IF	194	2	2	100.00
IF	204	2	2	100.00
TERNARY	170	2	2	100.00
IF	172	2	2	100.00
IF	288	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv' or '../src/lowrisc_prim_trivium_0.1/rtl/prim_trivium.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	189	(restore) ? 
-2-:	189	(wr_en_seed) ? 
-3-:	189	(update) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T1,T3,T6
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	285	((wr_en_seed & last_state_part)) ? 
-2-:	285	((wr_en_seed & (~last_state_part))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	204	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	170	((!update)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	172	if (last_state_part)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_trivium

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PrimTriviumPartialStateSeedWhileUpdate_A	2147483647	2261	0	0

PrimTriviumPartialStateSeedWhileUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2261	0	0
T1	360417	1	0	0
T2	342853	0	0	0
T3	85807	1	0	0
T6	444515	1	0	0
T7	131088	1	0	0
T8	250687	1	0	0
T9	290045	16	0	0
T10	0	1	0	0
T11	17983	0	0	0
T12	448001	0	0	0
T13	10632	1	0	0
T14	0	7	0	0
T32	0	1	0	0