Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	305	1			T11	7		T12	5		T35	8
all_values[1]	305	1			T11	7		T12	5		T35	8
all_values[2]	305	1			T11	7		T12	5		T35	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

489

1

T11

9

T12

10

T35

16

auto[1]

426

1

T11

12

T12

5

T35

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T11

18

T12

9

T35

18

auto[1]

297

1

T11

3

T12

6

T35

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104	1			T11	4		T35	6		T36	2
all_values[0]	auto[0]	auto[1]	46	1			T11	1		T12	1		T35	2
all_values[0]	auto[1]	auto[0]	102	1			T11	2		T12	3		T36	6
all_values[0]	auto[1]	auto[1]	53	1			T12	1		T23	2		T28	3
all_values[1]	auto[0]	auto[0]	108	1			T11	1		T12	3		T35	3
all_values[1]	auto[0]	auto[1]	46	1			T11	1		T12	1		T35	2
all_values[1]	auto[1]	auto[0]	98	1			T11	5		T35	3		T36	6
all_values[1]	auto[1]	auto[1]	53	1			T12	1		T23	1		T28	1
all_values[2]	auto[0]	auto[0]	128	1			T11	2		T12	3		T35	3
all_values[2]	auto[0]	auto[1]	57	1			T12	2		T23	2		T28	4
all_values[2]	auto[1]	auto[0]	78	1			T11	4		T35	3		T36	3
all_values[2]	auto[1]	auto[1]	42	1			T11	1		T35	2		T23	1