Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
43.42 34.14 57.11 11.73 0.00 38.97 100.00 61.97


Total tests in report: 214
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
38.93 38.93 33.83 33.83 51.40 51.40 10.88 10.88 0.00 0.00 38.12 38.12 92.67 92.67 45.63 45.63 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1242295543
40.37 1.43 34.00 0.17 52.61 1.21 11.05 0.17 0.00 0.00 38.60 0.48 93.19 0.52 53.10 7.46 /workspace/coverage/cover_reg_top/34.kmac_intr_test.1404290605
41.35 0.98 34.00 0.00 54.14 1.53 11.25 0.20 0.00 0.00 38.79 0.18 96.34 3.14 54.93 1.83 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.789549589
42.13 0.78 34.14 0.15 56.01 1.86 11.25 0.00 0.00 0.00 38.97 0.18 97.64 1.31 56.90 1.97 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3633873339
42.67 0.54 34.14 0.00 56.40 0.39 12.26 1.00 0.00 0.00 38.97 0.00 97.64 0.00 59.30 2.39 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1440993677
42.93 0.26 34.14 0.00 56.40 0.00 12.26 0.00 0.00 0.00 38.97 0.00 99.48 1.83 59.30 0.00 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.506252372
43.11 0.18 34.14 0.00 56.40 0.00 12.26 0.00 0.00 0.00 38.97 0.00 99.48 0.00 60.56 1.27 /workspace/coverage/cover_reg_top/21.kmac_intr_test.1511332090
43.24 0.13 34.14 0.00 56.53 0.13 12.35 0.09 0.00 0.00 38.97 0.00 100.00 0.52 60.70 0.14 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2714367877
43.31 0.06 34.14 0.00 56.53 0.00 12.37 0.03 0.00 0.00 38.97 0.00 100.00 0.00 61.13 0.42 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1370437149
43.37 0.06 34.14 0.00 56.53 0.00 12.37 0.00 0.00 0.00 38.97 0.00 100.00 0.00 61.55 0.42 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.565856276
43.42 0.05 34.14 0.00 56.76 0.23 12.37 0.00 0.00 0.00 38.97 0.00 100.00 0.00 61.69 0.14 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1607940627
43.46 0.05 34.14 0.00 57.08 0.33 12.37 0.00 0.00 0.00 38.97 0.00 100.00 0.00 61.69 0.00 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.4268476450
43.49 0.02 34.14 0.00 57.11 0.03 12.37 0.00 0.00 0.00 38.97 0.00 100.00 0.00 61.83 0.14 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3052881082
43.51 0.02 34.14 0.00 57.11 0.00 12.40 0.03 0.00 0.00 38.97 0.00 100.00 0.00 61.97 0.14 /workspace/coverage/cover_reg_top/26.kmac_intr_test.11375604

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.278354192
/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1470052725
/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1373413267
/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.826411802
/workspace/coverage/cover_reg_top/0.kmac_csr_rw.641445034
/workspace/coverage/cover_reg_top/0.kmac_intr_test.2695174479
/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4205636098
/workspace/coverage/cover_reg_top/0.kmac_mem_walk.1662978409
/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.662588776
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2266618683
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2704837029
/workspace/coverage/cover_reg_top/0.kmac_tl_errors.3345182428
/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1959622920
/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2966771363
/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1534552062
/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1866284286
/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1941317189
/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2940571677
/workspace/coverage/cover_reg_top/1.kmac_intr_test.216842430
/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3599234284
/workspace/coverage/cover_reg_top/1.kmac_mem_walk.4100862984
/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3424265540
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.159456722
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2438076389
/workspace/coverage/cover_reg_top/1.kmac_tl_errors.553271065
/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2674146350
/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2763539379
/workspace/coverage/cover_reg_top/10.kmac_csr_rw.1904880993
/workspace/coverage/cover_reg_top/10.kmac_intr_test.4226729006
/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1312545608
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3908343322
/workspace/coverage/cover_reg_top/10.kmac_tl_errors.431413068
/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3959686085
/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3688704175
/workspace/coverage/cover_reg_top/11.kmac_csr_rw.40333963
/workspace/coverage/cover_reg_top/11.kmac_intr_test.1850073456
/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2191353160
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.557355681
/workspace/coverage/cover_reg_top/11.kmac_tl_errors.726496633
/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2498398912
/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.4186500082
/workspace/coverage/cover_reg_top/12.kmac_csr_rw.1779053570
/workspace/coverage/cover_reg_top/12.kmac_intr_test.4231486508
/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3758516
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1147158107
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2569481829
/workspace/coverage/cover_reg_top/12.kmac_tl_errors.640032069
/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3778998981
/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3864416452
/workspace/coverage/cover_reg_top/13.kmac_csr_rw.4174429874
/workspace/coverage/cover_reg_top/13.kmac_intr_test.4070503429
/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.4219804362
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3544756425
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2778447143
/workspace/coverage/cover_reg_top/13.kmac_tl_errors.941160927
/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2706193140
/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.45685442
/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3375906668
/workspace/coverage/cover_reg_top/14.kmac_intr_test.2569843480
/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4038115174
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.705030142
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.110793201
/workspace/coverage/cover_reg_top/14.kmac_tl_errors.2763325062
/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3834726674
/workspace/coverage/cover_reg_top/15.kmac_csr_rw.2805170629
/workspace/coverage/cover_reg_top/15.kmac_intr_test.2820139039
/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.957059880
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.686018925
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.929361744
/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2759579789
/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1785093544
/workspace/coverage/cover_reg_top/16.kmac_csr_rw.803059062
/workspace/coverage/cover_reg_top/16.kmac_intr_test.2340200634
/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1223723146
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2240136355
/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2198585076
/workspace/coverage/cover_reg_top/17.kmac_csr_rw.890260220
/workspace/coverage/cover_reg_top/17.kmac_intr_test.608294274
/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3144088111
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4083659900
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2961309421
/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3752538764
/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.557161972
/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2203981481
/workspace/coverage/cover_reg_top/18.kmac_csr_rw.986370732
/workspace/coverage/cover_reg_top/18.kmac_intr_test.2778600950
/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1592532391
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.650361668
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2239852148
/workspace/coverage/cover_reg_top/18.kmac_tl_errors.2920708505
/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3160110983
/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3814291629
/workspace/coverage/cover_reg_top/19.kmac_csr_rw.3482681241
/workspace/coverage/cover_reg_top/19.kmac_intr_test.245972426
/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1727847621
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3673181793
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4010744164
/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3810021767
/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4184173361
/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3896904466
/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3207327379
/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2433553555
/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.650800950
/workspace/coverage/cover_reg_top/2.kmac_csr_rw.1161062781
/workspace/coverage/cover_reg_top/2.kmac_intr_test.3863514977
/workspace/coverage/cover_reg_top/2.kmac_mem_walk.3960268491
/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3204637553
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3984258573
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.705588500
/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.775724475
/workspace/coverage/cover_reg_top/20.kmac_intr_test.1726330159
/workspace/coverage/cover_reg_top/22.kmac_intr_test.4155135139
/workspace/coverage/cover_reg_top/23.kmac_intr_test.792905448
/workspace/coverage/cover_reg_top/24.kmac_intr_test.2678228476
/workspace/coverage/cover_reg_top/25.kmac_intr_test.2861878036
/workspace/coverage/cover_reg_top/27.kmac_intr_test.2774553457
/workspace/coverage/cover_reg_top/28.kmac_intr_test.3977593511
/workspace/coverage/cover_reg_top/29.kmac_intr_test.1158319948
/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1438459398
/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.443624873
/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1415209714
/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.4149786305
/workspace/coverage/cover_reg_top/3.kmac_csr_rw.3893827627
/workspace/coverage/cover_reg_top/3.kmac_intr_test.2370987899
/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2860332060
/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3391072536
/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.788504007
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2004551973
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2759854942
/workspace/coverage/cover_reg_top/3.kmac_tl_errors.2219202120
/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3753051891
/workspace/coverage/cover_reg_top/30.kmac_intr_test.459090711
/workspace/coverage/cover_reg_top/31.kmac_intr_test.3513656122
/workspace/coverage/cover_reg_top/32.kmac_intr_test.4200328793
/workspace/coverage/cover_reg_top/33.kmac_intr_test.21704552
/workspace/coverage/cover_reg_top/35.kmac_intr_test.312163468
/workspace/coverage/cover_reg_top/36.kmac_intr_test.2112504081
/workspace/coverage/cover_reg_top/37.kmac_intr_test.1674242954
/workspace/coverage/cover_reg_top/38.kmac_intr_test.3264214153
/workspace/coverage/cover_reg_top/39.kmac_intr_test.1222486251
/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.36838588
/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1953783448
/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1026319860
/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.172347763
/workspace/coverage/cover_reg_top/4.kmac_csr_rw.3960464984
/workspace/coverage/cover_reg_top/4.kmac_intr_test.3640645772
/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2366912208
/workspace/coverage/cover_reg_top/4.kmac_mem_walk.1864834744
/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1850890008
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2339665779
/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3031038712
/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2226415422
/workspace/coverage/cover_reg_top/40.kmac_intr_test.4243871066
/workspace/coverage/cover_reg_top/41.kmac_intr_test.3733382433
/workspace/coverage/cover_reg_top/42.kmac_intr_test.1710776990
/workspace/coverage/cover_reg_top/43.kmac_intr_test.1465188105
/workspace/coverage/cover_reg_top/44.kmac_intr_test.380825254
/workspace/coverage/cover_reg_top/45.kmac_intr_test.2789580189
/workspace/coverage/cover_reg_top/46.kmac_intr_test.4025408976
/workspace/coverage/cover_reg_top/47.kmac_intr_test.1917602153
/workspace/coverage/cover_reg_top/48.kmac_intr_test.2444723217
/workspace/coverage/cover_reg_top/49.kmac_intr_test.3320720178
/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2649784098
/workspace/coverage/cover_reg_top/5.kmac_csr_rw.1087058719
/workspace/coverage/cover_reg_top/5.kmac_intr_test.2818271105
/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.475467843
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.576125798
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3520918488
/workspace/coverage/cover_reg_top/5.kmac_tl_errors.3872791231
/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2744365224
/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2139742795
/workspace/coverage/cover_reg_top/6.kmac_csr_rw.628627598
/workspace/coverage/cover_reg_top/6.kmac_intr_test.2587529271
/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.519062221
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1186175978
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1491535622
/workspace/coverage/cover_reg_top/6.kmac_tl_errors.2909307769
/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4012042650
/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3592098531
/workspace/coverage/cover_reg_top/7.kmac_csr_rw.2543702075
/workspace/coverage/cover_reg_top/7.kmac_intr_test.1746109223
/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3545698958
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.114938408
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2573397642
/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3111905181
/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1033766620
/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1820219130
/workspace/coverage/cover_reg_top/8.kmac_csr_rw.1114757065
/workspace/coverage/cover_reg_top/8.kmac_intr_test.3370496353
/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.885167498
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.117600355
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3064775316
/workspace/coverage/cover_reg_top/8.kmac_tl_errors.3616134145
/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1217266215
/workspace/coverage/cover_reg_top/9.kmac_csr_rw.3140257985
/workspace/coverage/cover_reg_top/9.kmac_intr_test.4036597953
/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4152888243
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2439046530
/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3459572516
/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1049116684



Total test records in report: 214
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4083659900 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 28670789 ps
T2 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1864834744 Mar 14 01:12:18 PM PDT 24 Mar 14 01:12:19 PM PDT 24 31304326 ps
T3 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1779053570 Mar 14 01:12:33 PM PDT 24 Mar 14 01:12:34 PM PDT 24 21252165 ps
T4 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1866284286 Mar 14 01:12:17 PM PDT 24 Mar 14 01:12:18 PM PDT 24 18384223 ps
T5 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2239852148 Mar 14 01:12:39 PM PDT 24 Mar 14 01:12:41 PM PDT 24 110641646 ps
T6 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1592532391 Mar 14 01:12:39 PM PDT 24 Mar 14 01:12:42 PM PDT 24 175781347 ps
T11 /workspace/coverage/cover_reg_top/34.kmac_intr_test.1404290605 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 24388382 ps
T7 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1242295543 Mar 14 01:12:34 PM PDT 24 Mar 14 01:12:38 PM PDT 24 1072794275 ps
T8 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4012042650 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:42 PM PDT 24 187417137 ps
T12 /workspace/coverage/cover_reg_top/6.kmac_intr_test.2587529271 Mar 14 01:12:33 PM PDT 24 Mar 14 01:12:34 PM PDT 24 49627723 ps
T32 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1223723146 Mar 14 01:12:39 PM PDT 24 Mar 14 01:12:42 PM PDT 24 108845832 ps
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T135 /workspace/coverage/cover_reg_top/14.kmac_intr_test.2569843480 Mar 14 01:12:37 PM PDT 24 Mar 14 01:12:38 PM PDT 24 16573030 ps
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T74 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2759579789 Mar 14 01:12:40 PM PDT 24 Mar 14 01:12:45 PM PDT 24 238029113 ps
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T149 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2198585076 Mar 14 01:12:40 PM PDT 24 Mar 14 01:12:43 PM PDT 24 388860055 ps
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T151 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.4219804362 Mar 14 01:12:37 PM PDT 24 Mar 14 01:12:39 PM PDT 24 28312163 ps
T152 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1727847621 Mar 14 01:12:37 PM PDT 24 Mar 14 01:12:39 PM PDT 24 27187340 ps
T153 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3872791231 Mar 14 01:12:20 PM PDT 24 Mar 14 01:12:22 PM PDT 24 351893421 ps
T154 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.826411802 Mar 14 01:11:55 PM PDT 24 Mar 14 01:11:58 PM PDT 24 33015206 ps
T155 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2805170629 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 26102878 ps
T156 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1087058719 Mar 14 01:12:21 PM PDT 24 Mar 14 01:12:22 PM PDT 24 30809896 ps
T157 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.640032069 Mar 14 01:12:33 PM PDT 24 Mar 14 01:12:34 PM PDT 24 120553859 ps
T158 /workspace/coverage/cover_reg_top/44.kmac_intr_test.380825254 Mar 14 01:12:53 PM PDT 24 Mar 14 01:12:55 PM PDT 24 40822214 ps
T159 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3758516 Mar 14 01:12:33 PM PDT 24 Mar 14 01:12:36 PM PDT 24 385136543 ps
T160 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.114938408 Mar 14 01:12:29 PM PDT 24 Mar 14 01:12:30 PM PDT 24 25022318 ps
T161 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.650361668 Mar 14 01:12:40 PM PDT 24 Mar 14 01:12:41 PM PDT 24 15414946 ps
T162 /workspace/coverage/cover_reg_top/41.kmac_intr_test.3733382433 Mar 14 01:12:54 PM PDT 24 Mar 14 01:12:55 PM PDT 24 27159580 ps
T163 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1470052725 Mar 14 01:11:53 PM PDT 24 Mar 14 01:12:15 PM PDT 24 3831138072 ps
T164 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.986370732 Mar 14 01:12:41 PM PDT 24 Mar 14 01:12:42 PM PDT 24 95539787 ps
T70 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3052881082 Mar 14 01:12:21 PM PDT 24 Mar 14 01:12:23 PM PDT 24 156798399 ps
T165 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2744365224 Mar 14 01:12:20 PM PDT 24 Mar 14 01:12:23 PM PDT 24 532995260 ps
T166 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1147158107 Mar 14 01:12:37 PM PDT 24 Mar 14 01:12:39 PM PDT 24 37950377 ps
T167 /workspace/coverage/cover_reg_top/9.kmac_intr_test.4036597953 Mar 14 01:12:40 PM PDT 24 Mar 14 01:12:41 PM PDT 24 31799040 ps
T168 /workspace/coverage/cover_reg_top/30.kmac_intr_test.459090711 Mar 14 01:12:40 PM PDT 24 Mar 14 01:12:41 PM PDT 24 91012081 ps
T169 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2444723217 Mar 14 01:13:00 PM PDT 24 Mar 14 01:13:01 PM PDT 24 34825291 ps
T170 /workspace/coverage/cover_reg_top/39.kmac_intr_test.1222486251 Mar 14 01:12:54 PM PDT 24 Mar 14 01:12:55 PM PDT 24 54438616 ps
T171 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.775724475 Mar 14 01:12:16 PM PDT 24 Mar 14 01:12:21 PM PDT 24 374665306 ps
T172 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3375906668 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 21560746 ps
T173 /workspace/coverage/cover_reg_top/37.kmac_intr_test.1674242954 Mar 14 01:12:34 PM PDT 24 Mar 14 01:12:34 PM PDT 24 27985258 ps
T51 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4205636098 Mar 14 01:11:56 PM PDT 24 Mar 14 01:11:58 PM PDT 24 50449007 ps
T174 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3814291629 Mar 14 01:12:37 PM PDT 24 Mar 14 01:12:39 PM PDT 24 85694081 ps
T175 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2573397642 Mar 14 01:12:36 PM PDT 24 Mar 14 01:12:38 PM PDT 24 92793430 ps
T176 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1491535622 Mar 14 01:12:36 PM PDT 24 Mar 14 01:12:37 PM PDT 24 217260035 ps
T73 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.565856276 Mar 14 01:12:39 PM PDT 24 Mar 14 01:12:45 PM PDT 24 241225043 ps
T177 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3688704175 Mar 14 01:12:36 PM PDT 24 Mar 14 01:12:39 PM PDT 24 177014543 ps
T178 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1186175978 Mar 14 01:12:33 PM PDT 24 Mar 14 01:12:34 PM PDT 24 29445512 ps
T179 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3893827627 Mar 14 01:12:17 PM PDT 24 Mar 14 01:12:18 PM PDT 24 177132293 ps
T180 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1904880993 Mar 14 01:12:39 PM PDT 24 Mar 14 01:12:40 PM PDT 24 20569119 ps
T181 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.431413068 Mar 14 01:12:35 PM PDT 24 Mar 14 01:12:37 PM PDT 24 45647526 ps
T182 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.117600355 Mar 14 01:12:34 PM PDT 24 Mar 14 01:12:35 PM PDT 24 54529731 ps
T183 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1161062781 Mar 14 01:12:19 PM PDT 24 Mar 14 01:12:20 PM PDT 24 52047072 ps
T184 /workspace/coverage/cover_reg_top/2.kmac_intr_test.3863514977 Mar 14 01:12:19 PM PDT 24 Mar 14 01:12:20 PM PDT 24 14754992 ps
T185 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1710776990 Mar 14 01:12:46 PM PDT 24 Mar 14 01:12:47 PM PDT 24 40934769 ps
T186 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1217266215 Mar 14 01:12:33 PM PDT 24 Mar 14 01:12:34 PM PDT 24 143604546 ps
T187 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2139742795 Mar 14 01:12:35 PM PDT 24 Mar 14 01:12:37 PM PDT 24 81851063 ps
T188 /workspace/coverage/cover_reg_top/20.kmac_intr_test.1726330159 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 16941725 ps
T189 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1312545608 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 23206165 ps
T190 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4038115174 Mar 14 01:12:42 PM PDT 24 Mar 14 01:12:45 PM PDT 24 942453150 ps
T191 /workspace/coverage/cover_reg_top/38.kmac_intr_test.3264214153 Mar 14 01:12:53 PM PDT 24 Mar 14 01:12:55 PM PDT 24 15291143 ps
T192 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2240136355 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:40 PM PDT 24 63178468 ps
T193 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1953783448 Mar 14 01:12:21 PM PDT 24 Mar 14 01:12:43 PM PDT 24 1471732116 ps
T194 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3031038712 Mar 14 01:12:16 PM PDT 24 Mar 14 01:12:18 PM PDT 24 100276092 ps
T195 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2191353160 Mar 14 01:12:32 PM PDT 24 Mar 14 01:12:34 PM PDT 24 75943638 ps
T196 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.890260220 Mar 14 01:12:33 PM PDT 24 Mar 14 01:12:34 PM PDT 24 13706017 ps
T197 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.726496633 Mar 14 01:12:31 PM PDT 24 Mar 14 01:12:34 PM PDT 24 263184450 ps
T52 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2860332060 Mar 14 01:12:20 PM PDT 24 Mar 14 01:12:21 PM PDT 24 50017458 ps
T198 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3810021767 Mar 14 01:12:37 PM PDT 24 Mar 14 01:12:40 PM PDT 24 115822727 ps
T199 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.557161972 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:43 PM PDT 24 835899681 ps
T200 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2789580189 Mar 14 01:12:47 PM PDT 24 Mar 14 01:12:48 PM PDT 24 37768700 ps
T201 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1941317189 Mar 14 01:12:20 PM PDT 24 Mar 14 01:12:22 PM PDT 24 188259030 ps
T202 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2203981481 Mar 14 01:12:40 PM PDT 24 Mar 14 01:12:42 PM PDT 24 153101978 ps
T203 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3864416452 Mar 14 01:12:34 PM PDT 24 Mar 14 01:12:37 PM PDT 24 295201697 ps
T204 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.4186500082 Mar 14 01:12:35 PM PDT 24 Mar 14 01:12:38 PM PDT 24 72886061 ps
T205 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2909307769 Mar 14 01:12:34 PM PDT 24 Mar 14 01:12:37 PM PDT 24 235114079 ps
T206 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2778447143 Mar 14 01:12:34 PM PDT 24 Mar 14 01:12:36 PM PDT 24 106161473 ps
T207 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3520918488 Mar 14 01:12:19 PM PDT 24 Mar 14 01:12:22 PM PDT 24 85584341 ps
T208 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1850890008 Mar 14 01:12:21 PM PDT 24 Mar 14 01:12:24 PM PDT 24 224371212 ps
T209 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3834726674 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 28109478 ps
T210 /workspace/coverage/cover_reg_top/4.kmac_intr_test.3640645772 Mar 14 01:12:20 PM PDT 24 Mar 14 01:12:21 PM PDT 24 73188903 ps
T211 /workspace/coverage/cover_reg_top/35.kmac_intr_test.312163468 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 37400904 ps
T212 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.885167498 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:41 PM PDT 24 177155555 ps
T213 /workspace/coverage/cover_reg_top/36.kmac_intr_test.2112504081 Mar 14 01:12:38 PM PDT 24 Mar 14 01:12:39 PM PDT 24 13314455 ps
T214 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.957059880 Mar 14 01:12:40 PM PDT 24 Mar 14 01:12:42 PM PDT 24 24669901 ps

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1242295543
Short name T7
Test name
Test status
Simulation time 1072794275 ps
CPU time 4.09 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215820 kb
Host smart-987f2003-2844-484b-957b-4be936143f75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242295543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1242
295543 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.1404290605
Short name T11
Test name
Test status
Simulation time 24388382 ps
CPU time 0.84 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215704 kb
Host smart-5a083def-9b83-42c7-a4ad-918148e23d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404290605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1404290605 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.789549589
Short name T57
Test name
Test status
Simulation time 416699081 ps
CPU time 2.65 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 218936 kb
Host smart-9641456b-e84b-4728-a578-41f91ba3d62c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789549589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac
_shadow_reg_errors_with_csr_rw.789549589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3633873339
Short name T9
Test name
Test status
Simulation time 968916314 ps
CPU time 4.15 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215992 kb
Host smart-6b83966d-dce8-4d34-82de-a5305208f2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633873339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3633873339 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.1440993677
Short name T10
Test name
Test status
Simulation time 67822730 ps
CPU time 2.71 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 219280 kb
Host smart-963720e1-4b1a-4c20-911f-122fd2e59fcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440993677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac
_shadow_reg_errors_with_csr_rw.1440993677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.506252372
Short name T16
Test name
Test status
Simulation time 70631671 ps
CPU time 1.42 seconds
Started Mar 14 01:12:18 PM PDT 24
Finished Mar 14 01:12:20 PM PDT 24
Peak memory 215876 kb
Host smart-853ea295-cb4b-48a3-b8b8-f3b7c434e047
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506252372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial
_access.506252372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.1511332090
Short name T23
Test name
Test status
Simulation time 17552175 ps
CPU time 0.83 seconds
Started Mar 14 01:12:28 PM PDT 24
Finished Mar 14 01:12:29 PM PDT 24
Peak memory 215684 kb
Host smart-fa1d6f63-88dd-47d0-b09d-b83e1bea4b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511332090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1511332090 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2714367877
Short name T34
Test name
Test status
Simulation time 32508880 ps
CPU time 1.6 seconds
Started Mar 14 01:12:32 PM PDT 24
Finished Mar 14 01:12:33 PM PDT 24
Peak memory 215972 kb
Host smart-c11ab214-44b7-4c88-a935-338e4c2fac34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714367877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.2714367877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1370437149
Short name T65
Test name
Test status
Simulation time 134058553 ps
CPU time 3.07 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215912 kb
Host smart-0e842916-49d0-49e2-a6b7-a85c822ac11d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370437149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.13704
37149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.565856276
Short name T73
Test name
Test status
Simulation time 241225043 ps
CPU time 5.33 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:45 PM PDT 24
Peak memory 215872 kb
Host smart-bc45df2a-8a06-44bb-8b8c-d37e8501a4da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565856276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.56585
6276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1607940627
Short name T37
Test name
Test status
Simulation time 192914619 ps
CPU time 1.2 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215992 kb
Host smart-b2230fa1-667e-47db-a38f-f42862f08563
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607940627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.1607940627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.4268476450
Short name T59
Test name
Test status
Simulation time 120122887 ps
CPU time 2.57 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 216036 kb
Host smart-30d43f18-3f37-4b87-abbe-91f2aa0e8773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268476450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.4268476450 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3052881082
Short name T70
Test name
Test status
Simulation time 156798399 ps
CPU time 1.58 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:23 PM PDT 24
Peak memory 216044 kb
Host smart-ecf29529-17e1-4fdc-82c1-9a692a3d4fff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052881082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3052881082 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.11375604
Short name T89
Test name
Test status
Simulation time 34097296 ps
CPU time 0.8 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 215688 kb
Host smart-bc1da507-f33b-4609-af87-7458bd28bc3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11375604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.11375604 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.278354192
Short name T64
Test name
Test status
Simulation time 1809771646 ps
CPU time 9.23 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:12:04 PM PDT 24
Peak memory 215912 kb
Host smart-c6f450d1-a271-4e08-9f9b-88aeb8f20bd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278354192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.27835419
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.1470052725
Short name T163
Test name
Test status
Simulation time 3831138072 ps
CPU time 20.63 seconds
Started Mar 14 01:11:53 PM PDT 24
Finished Mar 14 01:12:15 PM PDT 24
Peak memory 215888 kb
Host smart-8f5eb9a6-7027-45bd-8558-2d5fd576e277
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470052725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1470052
725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1373413267
Short name T142
Test name
Test status
Simulation time 36638405 ps
CPU time 0.99 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 215704 kb
Host smart-db8ea7fd-63a6-431d-9837-7cc2ad0463f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373413267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1373413
267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.826411802
Short name T154
Test name
Test status
Simulation time 33015206 ps
CPU time 2.38 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:58 PM PDT 24
Peak memory 219320 kb
Host smart-5d15f541-261d-4cd8-9e1f-0839d5e8715a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826411802 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.826411802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.641445034
Short name T63
Test name
Test status
Simulation time 24708842 ps
CPU time 1.01 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:11:56 PM PDT 24
Peak memory 215760 kb
Host smart-8e923ede-53a1-48e9-8545-03fc4944af67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641445034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.641445034 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2695174479
Short name T95
Test name
Test status
Simulation time 18077515 ps
CPU time 0.84 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:56 PM PDT 24
Peak memory 215644 kb
Host smart-b56090ed-f158-4cd9-b4aa-da9ac39231bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695174479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2695174479 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4205636098
Short name T51
Test name
Test status
Simulation time 50449007 ps
CPU time 1.17 seconds
Started Mar 14 01:11:56 PM PDT 24
Finished Mar 14 01:11:58 PM PDT 24
Peak memory 215924 kb
Host smart-f6c688d1-2519-43e1-981b-e7c1638d9e2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205636098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.4205636098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.1662978409
Short name T128
Test name
Test status
Simulation time 12301705 ps
CPU time 0.74 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 215796 kb
Host smart-6958165e-a595-40eb-b8e6-b07125c6d91e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662978409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.1662978409
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.662588776
Short name T114
Test name
Test status
Simulation time 63796165 ps
CPU time 2.11 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:58 PM PDT 24
Peak memory 215900 kb
Host smart-973ffbfe-3304-49aa-a78f-1aa02d3c8ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662588776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_
outstanding.662588776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2266618683
Short name T38
Test name
Test status
Simulation time 103723446 ps
CPU time 1.43 seconds
Started Mar 14 01:11:53 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 217376 kb
Host smart-19a0b718-bfea-42be-b8dd-668737f45347
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266618683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2266618683 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2704837029
Short name T146
Test name
Test status
Simulation time 112164168 ps
CPU time 2.88 seconds
Started Mar 14 01:11:55 PM PDT 24
Finished Mar 14 01:11:59 PM PDT 24
Peak memory 218736 kb
Host smart-33d9e53e-9958-4aa5-a430-e1988ab4f6be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704837029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2704837029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3345182428
Short name T60
Test name
Test status
Simulation time 88392130 ps
CPU time 2.14 seconds
Started Mar 14 01:11:52 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 216044 kb
Host smart-b56ff67c-329c-44b8-87b6-6c8cba6fcfa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345182428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3345182428 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.1959622920
Short name T75
Test name
Test status
Simulation time 337224988 ps
CPU time 4.97 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:12:00 PM PDT 24
Peak memory 215904 kb
Host smart-0eec9c3f-84e8-4786-8a09-3ad6fe50a5a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959622920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.19596
22920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2966771363
Short name T93
Test name
Test status
Simulation time 88221804 ps
CPU time 4.67 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:26 PM PDT 24
Peak memory 215920 kb
Host smart-fd4f8967-83a5-4e51-b034-a54dcbd95d64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966771363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2966771
363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1534552062
Short name T112
Test name
Test status
Simulation time 322546051 ps
CPU time 14.69 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:32 PM PDT 24
Peak memory 215808 kb
Host smart-6793626d-6a1b-4135-9be1-e3191f20c4cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534552062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1534552
062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1866284286
Short name T4
Test name
Test status
Simulation time 18384223 ps
CPU time 1.12 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 215804 kb
Host smart-470c2d4f-a527-462a-b1b9-07b91ca00f9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866284286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1866284
286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1941317189
Short name T201
Test name
Test status
Simulation time 188259030 ps
CPU time 1.66 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 219884 kb
Host smart-6069292a-d48d-49b1-8720-31ddbc0a56c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941317189 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1941317189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2940571677
Short name T82
Test name
Test status
Simulation time 53141502 ps
CPU time 0.95 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 215580 kb
Host smart-ba1258d0-551b-4327-8b88-19321fab0108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940571677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2940571677 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.216842430
Short name T150
Test name
Test status
Simulation time 23090391 ps
CPU time 0.78 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 215728 kb
Host smart-928a4850-7eb5-496f-accf-63a9470c80b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216842430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.216842430 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3599234284
Short name T31
Test name
Test status
Simulation time 128949892 ps
CPU time 1.52 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:19 PM PDT 24
Peak memory 215908 kb
Host smart-794a2f88-24e3-4f67-8e34-5c9f23d07d9b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599234284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.3599234284 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.4100862984
Short name T123
Test name
Test status
Simulation time 29871075 ps
CPU time 0.74 seconds
Started Mar 14 01:11:59 PM PDT 24
Finished Mar 14 01:12:00 PM PDT 24
Peak memory 215696 kb
Host smart-0f48728d-3012-4f5d-bdc1-8e122627be53
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100862984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.4100862984
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3424265540
Short name T53
Test name
Test status
Simulation time 41828753 ps
CPU time 1.43 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 215912 kb
Host smart-d806451a-6648-4873-8c9e-fe15dec56a00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424265540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.3424265540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.159456722
Short name T98
Test name
Test status
Simulation time 44387194 ps
CPU time 1.26 seconds
Started Mar 14 01:11:53 PM PDT 24
Finished Mar 14 01:11:55 PM PDT 24
Peak memory 216496 kb
Host smart-eb90a01a-6477-4cd1-a4ce-7f06ea8798f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159456722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e
rrors.159456722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2438076389
Short name T49
Test name
Test status
Simulation time 78266293 ps
CPU time 1.67 seconds
Started Mar 14 01:11:54 PM PDT 24
Finished Mar 14 01:11:56 PM PDT 24
Peak memory 215984 kb
Host smart-74c87eb7-f863-44f6-8b68-94abc3ec4b57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438076389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.2438076389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.553271065
Short name T17
Test name
Test status
Simulation time 96214676 ps
CPU time 2.84 seconds
Started Mar 14 01:12:18 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 216064 kb
Host smart-2904b9b5-6ef0-47f6-9213-c12137e26e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553271065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.553271065 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2674146350
Short name T33
Test name
Test status
Simulation time 1368648965 ps
CPU time 2.92 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215848 kb
Host smart-939e26b5-3b09-4b6d-a7b1-ce273d99fae7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674146350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.26741
46350 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2763539379
Short name T113
Test name
Test status
Simulation time 94697998 ps
CPU time 2.57 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 221048 kb
Host smart-b655d36b-74fa-46e9-9b5d-54cb0e78ddab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763539379 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2763539379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1904880993
Short name T180
Test name
Test status
Simulation time 20569119 ps
CPU time 1.13 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 215960 kb
Host smart-40e13cd6-698a-49c0-a66a-29f1ffec94f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904880993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1904880993 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.4226729006
Short name T137
Test name
Test status
Simulation time 64423406 ps
CPU time 0.82 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215664 kb
Host smart-fa4d0fa5-404b-4bd4-86c4-c9a09ef620cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226729006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.4226729006 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1312545608
Short name T189
Test name
Test status
Simulation time 23206165 ps
CPU time 1.49 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215920 kb
Host smart-58882ab2-45e4-496c-8298-49763f9067d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312545608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.1312545608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3908343322
Short name T90
Test name
Test status
Simulation time 34858373 ps
CPU time 0.94 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215720 kb
Host smart-f224d187-d92d-4d30-aecb-d1b8316da2e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908343322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3908343322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.431413068
Short name T181
Test name
Test status
Simulation time 45647526 ps
CPU time 1.63 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 216056 kb
Host smart-945600d8-a50c-4681-953f-11cc38c699a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431413068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.431413068 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.3959686085
Short name T72
Test name
Test status
Simulation time 1668796483 ps
CPU time 5.53 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215924 kb
Host smart-f28e649d-637d-4d30-a1fe-84a4913b19f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959686085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3959
686085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3688704175
Short name T177
Test name
Test status
Simulation time 177014543 ps
CPU time 2.67 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 220336 kb
Host smart-2f2f018e-b92a-45d9-8288-09856a87d087
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688704175 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3688704175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.40333963
Short name T127
Test name
Test status
Simulation time 19944460 ps
CPU time 0.97 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215708 kb
Host smart-37faa488-6cf9-49e0-b96e-9b571957d271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.40333963 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.1850073456
Short name T134
Test name
Test status
Simulation time 180472434 ps
CPU time 0.85 seconds
Started Mar 14 01:12:31 PM PDT 24
Finished Mar 14 01:12:32 PM PDT 24
Peak memory 215640 kb
Host smart-e509924f-f134-4146-b7c7-8eb011fb03f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850073456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1850073456 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.2191353160
Short name T195
Test name
Test status
Simulation time 75943638 ps
CPU time 1.49 seconds
Started Mar 14 01:12:32 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 215856 kb
Host smart-c9fd825b-9771-400f-adf8-01760f037ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191353160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.2191353160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.557355681
Short name T56
Test name
Test status
Simulation time 1118606847 ps
CPU time 3.07 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 216240 kb
Host smart-f441b63f-1380-4d5e-a955-deb850902220
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557355681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac
_shadow_reg_errors_with_csr_rw.557355681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.726496633
Short name T197
Test name
Test status
Simulation time 263184450 ps
CPU time 2.1 seconds
Started Mar 14 01:12:31 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 216092 kb
Host smart-3e03cdb5-c898-4ea8-b115-221f6143db7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726496633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.726496633 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2498398912
Short name T40
Test name
Test status
Simulation time 106761585 ps
CPU time 2.88 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 215868 kb
Host smart-dca83005-7f8e-44e7-bee2-59b05c611ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498398912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2498
398912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.4186500082
Short name T204
Test name
Test status
Simulation time 72886061 ps
CPU time 2.54 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 220664 kb
Host smart-3206b652-efdf-4ab4-9623-0988bc3726b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186500082 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.4186500082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1779053570
Short name T3
Test name
Test status
Simulation time 21252165 ps
CPU time 0.94 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 215656 kb
Host smart-f9bdde04-d315-441d-a63a-66aac67a4215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779053570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1779053570 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.4231486508
Short name T139
Test name
Test status
Simulation time 21165209 ps
CPU time 0.76 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:35 PM PDT 24
Peak memory 215720 kb
Host smart-bf3f938d-0ef6-44cb-82dc-0fd1d0572abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231486508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.4231486508 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3758516
Short name T159
Test name
Test status
Simulation time 385136543 ps
CPU time 2.17 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215784 kb
Host smart-f379b0b5-53e5-4fe5-b079-8574d6968890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_o
utstanding.3758516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1147158107
Short name T166
Test name
Test status
Simulation time 37950377 ps
CPU time 1.27 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 216388 kb
Host smart-671c9dd2-0cf7-4cfd-823e-e9cef6ee56ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147158107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.1147158107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2569481829
Short name T143
Test name
Test status
Simulation time 44384650 ps
CPU time 2.4 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 216464 kb
Host smart-6797dee4-d1e4-401e-a7e9-b8c701705f82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569481829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.2569481829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.640032069
Short name T157
Test name
Test status
Simulation time 120553859 ps
CPU time 1.56 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 216048 kb
Host smart-66223a6b-4e55-4bab-a73a-edc29e749019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640032069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.640032069 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3778998981
Short name T26
Test name
Test status
Simulation time 64165404 ps
CPU time 2.51 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215944 kb
Host smart-c2410114-9ca3-4d8b-af48-565a9e1d16ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778998981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3778
998981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3864416452
Short name T203
Test name
Test status
Simulation time 295201697 ps
CPU time 2.35 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 221896 kb
Host smart-b5f736b4-34dd-46bf-9399-0c26537a50f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864416452 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3864416452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.4174429874
Short name T88
Test name
Test status
Simulation time 132402279 ps
CPU time 1.14 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215920 kb
Host smart-f5c7b947-cdfe-4ea6-85b4-2eec00a3ef17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174429874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.4174429874 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.4070503429
Short name T45
Test name
Test status
Simulation time 37722767 ps
CPU time 0.8 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215708 kb
Host smart-16f1ead0-608f-4700-9583-3fb9276e9d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070503429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4070503429 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.4219804362
Short name T151
Test name
Test status
Simulation time 28312163 ps
CPU time 1.57 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215976 kb
Host smart-bdcead87-3958-4c1c-bbbe-ceafa99ea194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219804362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.4219804362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3544756425
Short name T24
Test name
Test status
Simulation time 117410559 ps
CPU time 0.98 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215800 kb
Host smart-f7c1d992-efd9-4281-9dd8-79363c799b28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544756425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3544756425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.2778447143
Short name T206
Test name
Test status
Simulation time 106161473 ps
CPU time 1.54 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 216140 kb
Host smart-93108436-6bc3-4718-9dc7-d248d5e0353c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778447143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.2778447143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.941160927
Short name T15
Test name
Test status
Simulation time 37290131 ps
CPU time 2.63 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215932 kb
Host smart-ec33159d-08ba-491d-ba41-32b9b6bebe7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941160927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.941160927 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.2706193140
Short name T78
Test name
Test status
Simulation time 199688040 ps
CPU time 4.65 seconds
Started Mar 14 01:12:32 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215920 kb
Host smart-9f859047-a5c8-46f1-8e85-d0b1bf6b2c81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706193140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2706
193140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.45685442
Short name T18
Test name
Test status
Simulation time 25565519 ps
CPU time 1.63 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 217136 kb
Host smart-40fc15cc-b907-4849-839b-2d4541b2530d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45685442 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.45685442 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.3375906668
Short name T172
Test name
Test status
Simulation time 21560746 ps
CPU time 1 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215720 kb
Host smart-1762edbe-84b9-4a67-b36d-8ec72fff9614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375906668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3375906668 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.2569843480
Short name T135
Test name
Test status
Simulation time 16573030 ps
CPU time 0.79 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215680 kb
Host smart-ccf102b3-b22b-44c4-87b5-207141f4882b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569843480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2569843480 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.4038115174
Short name T190
Test name
Test status
Simulation time 942453150 ps
CPU time 2.68 seconds
Started Mar 14 01:12:42 PM PDT 24
Finished Mar 14 01:12:45 PM PDT 24
Peak memory 215952 kb
Host smart-9ee969cf-f248-4114-b968-96327b92478f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038115174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.4038115174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.705030142
Short name T130
Test name
Test status
Simulation time 82226347 ps
CPU time 1.12 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 216352 kb
Host smart-057bdf4f-2126-4761-b4e4-8fe1737cda7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705030142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_
errors.705030142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.110793201
Short name T115
Test name
Test status
Simulation time 121557351 ps
CPU time 1.89 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 218760 kb
Host smart-cbd86a4a-2eb6-46f2-ab3a-61a29c5f5505
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110793201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.110793201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.2763325062
Short name T20
Test name
Test status
Simulation time 76299297 ps
CPU time 2.1 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215996 kb
Host smart-8de1395b-ba72-4aaa-8d29-2d2388672276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763325062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2763325062 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3834726674
Short name T209
Test name
Test status
Simulation time 28109478 ps
CPU time 1.7 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 217296 kb
Host smart-df85b339-bc0f-4747-be62-a5ca67c4469c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834726674 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3834726674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2805170629
Short name T155
Test name
Test status
Simulation time 26102878 ps
CPU time 1.03 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215704 kb
Host smart-be94c2c7-10e1-45ec-8a81-e9201cbeb9de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805170629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2805170629 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.2820139039
Short name T86
Test name
Test status
Simulation time 37025357 ps
CPU time 0.8 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215664 kb
Host smart-83402ea0-e74b-46e1-ad58-89f14ce7a8ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820139039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2820139039 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.957059880
Short name T214
Test name
Test status
Simulation time 24669901 ps
CPU time 1.58 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 215852 kb
Host smart-370cc9ec-d0b1-4784-b7f0-cb59ba7a8c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957059880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr
_outstanding.957059880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.686018925
Short name T80
Test name
Test status
Simulation time 56041112 ps
CPU time 0.94 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215800 kb
Host smart-dd6c0a40-1c76-4447-b0ae-604f3518ece4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686018925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_
errors.686018925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.929361744
Short name T132
Test name
Test status
Simulation time 50999973 ps
CPU time 1.72 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 219168 kb
Host smart-248b4ee2-07c3-4e51-8125-04403cdb008a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929361744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac
_shadow_reg_errors_with_csr_rw.929361744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2759579789
Short name T74
Test name
Test status
Simulation time 238029113 ps
CPU time 5.02 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:45 PM PDT 24
Peak memory 215836 kb
Host smart-e9c91ecc-1890-42e2-ad88-7e85fba0fd33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759579789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2759
579789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1785093544
Short name T111
Test name
Test status
Simulation time 88888868 ps
CPU time 2.52 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 221040 kb
Host smart-d00e8807-2f94-4b6e-a2fd-d431547a9093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785093544 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.1785093544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.803059062
Short name T55
Test name
Test status
Simulation time 47327552 ps
CPU time 1.05 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215860 kb
Host smart-8bf3eaa5-ccfa-4566-9a9b-1664f99fb4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803059062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.803059062 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2340200634
Short name T119
Test name
Test status
Simulation time 21118614 ps
CPU time 0.77 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 215660 kb
Host smart-fd86feba-aa0e-41f4-941f-80b88991d7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340200634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2340200634 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1223723146
Short name T32
Test name
Test status
Simulation time 108845832 ps
CPU time 2.39 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 215900 kb
Host smart-0e72c720-c747-433f-a97d-d1ee699f7623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223723146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.1223723146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2240136355
Short name T192
Test name
Test status
Simulation time 63178468 ps
CPU time 1.22 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 216348 kb
Host smart-1aa66648-a6be-4e9c-832f-47866fc04433
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240136355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2240136355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2198585076
Short name T149
Test name
Test status
Simulation time 388860055 ps
CPU time 2.87 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:43 PM PDT 24
Peak memory 220620 kb
Host smart-9fba24db-d5cf-46f4-b370-eabc0be8dc90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198585076 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2198585076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.890260220
Short name T196
Test name
Test status
Simulation time 13706017 ps
CPU time 0.95 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 215656 kb
Host smart-82b0b4d7-d8cf-40fc-b9d2-b11aa8f00b23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890260220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.890260220 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.608294274
Short name T94
Test name
Test status
Simulation time 18732038 ps
CPU time 0.83 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215560 kb
Host smart-e0317f87-65bb-44f5-aeff-22f2ade28e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608294274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.608294274 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3144088111
Short name T54
Test name
Test status
Simulation time 1237929994 ps
CPU time 1.69 seconds
Started Mar 14 01:12:46 PM PDT 24
Finished Mar 14 01:12:48 PM PDT 24
Peak memory 215836 kb
Host smart-eff0423d-51e9-49b3-965e-4907ebb54263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144088111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.3144088111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.4083659900
Short name T1
Test name
Test status
Simulation time 28670789 ps
CPU time 0.98 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 216080 kb
Host smart-a8104223-b0da-49f4-a96c-2d8246fce224
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083659900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.4083659900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2961309421
Short name T148
Test name
Test status
Simulation time 134848295 ps
CPU time 2.7 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:43 PM PDT 24
Peak memory 215952 kb
Host smart-f4ccc65e-4288-4b8d-964d-96b676e1f527
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961309421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2961309421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.3752538764
Short name T62
Test name
Test status
Simulation time 49053915 ps
CPU time 1.72 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 216016 kb
Host smart-874993d1-f12c-4f1d-a529-f6b2f0700a34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752538764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3752538764 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.557161972
Short name T199
Test name
Test status
Simulation time 835899681 ps
CPU time 5.14 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:43 PM PDT 24
Peak memory 215824 kb
Host smart-53c7825c-bfe6-4533-be79-abdd040a902c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557161972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.55716
1972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2203981481
Short name T202
Test name
Test status
Simulation time 153101978 ps
CPU time 2.19 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 220368 kb
Host smart-c80a2f28-bac8-4317-8867-1e75dabb9797
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203981481 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2203981481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.986370732
Short name T164
Test name
Test status
Simulation time 95539787 ps
CPU time 1.2 seconds
Started Mar 14 01:12:41 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 215892 kb
Host smart-aa3842f4-4520-4963-a754-f2e89eca38b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986370732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.986370732 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.2778600950
Short name T68
Test name
Test status
Simulation time 16926599 ps
CPU time 0.84 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215688 kb
Host smart-6e455d88-3227-47a1-8070-1a6c947f60c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778600950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2778600950 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1592532391
Short name T6
Test name
Test status
Simulation time 175781347 ps
CPU time 2.12 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 215900 kb
Host smart-a556a379-a4f8-45ba-b847-4e285a5c3ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592532391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.1592532391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.650361668
Short name T161
Test name
Test status
Simulation time 15414946 ps
CPU time 0.87 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215616 kb
Host smart-d2d14235-2730-47c6-9305-ced7f71975e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650361668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.650361668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2239852148
Short name T5
Test name
Test status
Simulation time 110641646 ps
CPU time 1.62 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 219488 kb
Host smart-36fa96db-29b4-457b-9dc4-7488696c8be8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239852148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.2239852148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.2920708505
Short name T14
Test name
Test status
Simulation time 129506176 ps
CPU time 2.42 seconds
Started Mar 14 01:12:41 PM PDT 24
Finished Mar 14 01:12:43 PM PDT 24
Peak memory 215892 kb
Host smart-e4ec80a9-d4d3-4563-9b38-c2bceb4a0366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920708505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2920708505 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3160110983
Short name T76
Test name
Test status
Simulation time 349010794 ps
CPU time 4.97 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:45 PM PDT 24
Peak memory 215928 kb
Host smart-c44f2c8c-aab8-4062-9ed2-78dd8a0691e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160110983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3160
110983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3814291629
Short name T174
Test name
Test status
Simulation time 85694081 ps
CPU time 2.48 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 220568 kb
Host smart-0a6d2fd4-3325-4a1f-a928-594d5e078dc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814291629 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3814291629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3482681241
Short name T109
Test name
Test status
Simulation time 58558687 ps
CPU time 1.14 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215904 kb
Host smart-9e9f50bd-0b4d-4df5-9c62-20969967b87c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482681241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3482681241 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.245972426
Short name T103
Test name
Test status
Simulation time 15825339 ps
CPU time 0.79 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 215728 kb
Host smart-8708a7e9-6673-43a5-ae40-5bfaab715aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245972426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.245972426 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1727847621
Short name T152
Test name
Test status
Simulation time 27187340 ps
CPU time 1.51 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215900 kb
Host smart-1a362194-92ff-4025-87bf-5352106808e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727847621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.1727847621 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3673181793
Short name T58
Test name
Test status
Simulation time 155544623 ps
CPU time 1.42 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 217420 kb
Host smart-08ed3b50-f580-4561-b019-7443495fc851
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673181793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3673181793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.4010744164
Short name T116
Test name
Test status
Simulation time 133776911 ps
CPU time 2.84 seconds
Started Mar 14 01:12:41 PM PDT 24
Finished Mar 14 01:12:44 PM PDT 24
Peak memory 216420 kb
Host smart-897e1d60-525c-469c-ace8-ef85a776f319
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010744164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.4010744164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.3810021767
Short name T198
Test name
Test status
Simulation time 115822727 ps
CPU time 3.1 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 215976 kb
Host smart-3cfb6136-6ef9-4570-b1e9-1f1ecb838195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810021767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3810021767 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4184173361
Short name T79
Test name
Test status
Simulation time 216277048 ps
CPU time 2.59 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215828 kb
Host smart-0320f00c-6e82-4b7b-8ce5-a03316f0ea61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184173361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4184
173361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.3896904466
Short name T136
Test name
Test status
Simulation time 468668490 ps
CPU time 4.37 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:24 PM PDT 24
Peak memory 215872 kb
Host smart-37ba309a-a03e-494c-8656-7743c4416f8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896904466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3896904
466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.3207327379
Short name T126
Test name
Test status
Simulation time 5765492001 ps
CPU time 23.47 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:43 PM PDT 24
Peak memory 215944 kb
Host smart-9a60f556-13ae-4f04-aac2-1ff826232548
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207327379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.3207327
379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.2433553555
Short name T145
Test name
Test status
Simulation time 31797366 ps
CPU time 1.12 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 215912 kb
Host smart-f8445d94-61b2-4bbe-92fe-7d792c8a87e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433553555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.2433553
555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.650800950
Short name T138
Test name
Test status
Simulation time 81840047 ps
CPU time 1.63 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 216912 kb
Host smart-aa2c87cf-e45f-4acf-ab54-600a99f2d1b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650800950 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.650800950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1161062781
Short name T183
Test name
Test status
Simulation time 52047072 ps
CPU time 1.09 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:20 PM PDT 24
Peak memory 215848 kb
Host smart-328a67f9-f343-4e73-83c1-7368fe07aa62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161062781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1161062781 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.3863514977
Short name T184
Test name
Test status
Simulation time 14754992 ps
CPU time 0.83 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:20 PM PDT 24
Peak memory 215656 kb
Host smart-d2a54a62-f2f5-4131-b0ed-f56bc93b0a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863514977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3863514977 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3960268491
Short name T118
Test name
Test status
Simulation time 15120706 ps
CPU time 0.75 seconds
Started Mar 14 01:12:18 PM PDT 24
Finished Mar 14 01:12:19 PM PDT 24
Peak memory 215688 kb
Host smart-0ac7d815-56a9-4bcb-8d78-e0cb2829acee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960268491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3960268491
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3204637553
Short name T91
Test name
Test status
Simulation time 36664255 ps
CPU time 2.16 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:23 PM PDT 24
Peak memory 215828 kb
Host smart-1e5a565b-607e-44f6-a340-d79dd3ff302d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204637553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.3204637553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3984258573
Short name T43
Test name
Test status
Simulation time 46062182 ps
CPU time 1.24 seconds
Started Mar 14 01:12:16 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 216512 kb
Host smart-2870d747-1d4f-4568-a91d-5026800c11ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984258573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3984258573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.705588500
Short name T107
Test name
Test status
Simulation time 167541054 ps
CPU time 1.78 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:19 PM PDT 24
Peak memory 215960 kb
Host smart-76afd330-54ae-4b35-8777-8606b3b61a80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705588500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_
shadow_reg_errors_with_csr_rw.705588500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.775724475
Short name T171
Test name
Test status
Simulation time 374665306 ps
CPU time 5.32 seconds
Started Mar 14 01:12:16 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 215924 kb
Host smart-f3692b52-1a05-41c7-9d52-b8cf5ccc261f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775724475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.775724
475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.1726330159
Short name T188
Test name
Test status
Simulation time 16941725 ps
CPU time 0.87 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215708 kb
Host smart-5ca962fa-045a-495a-b883-29adf4365d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726330159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1726330159 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.4155135139
Short name T140
Test name
Test status
Simulation time 35169283 ps
CPU time 0.76 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215728 kb
Host smart-8243c98a-c3a3-4343-9867-26feefe977bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155135139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.4155135139 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.792905448
Short name T28
Test name
Test status
Simulation time 39735969 ps
CPU time 0.78 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215704 kb
Host smart-d59198ec-40a0-440a-ac10-13ed9bff1f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792905448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.792905448 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2678228476
Short name T105
Test name
Test status
Simulation time 18575332 ps
CPU time 0.84 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215616 kb
Host smart-d7c3ed74-fd7e-43b9-9239-98178b8a9cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678228476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2678228476 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2861878036
Short name T144
Test name
Test status
Simulation time 48189323 ps
CPU time 0.82 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215728 kb
Host smart-75aa8e78-4a67-49e5-bff6-22320150343c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861878036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2861878036 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2774553457
Short name T48
Test name
Test status
Simulation time 27544320 ps
CPU time 0.76 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215728 kb
Host smart-216fa6f4-7d55-4c75-9161-8017b57ac8e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774553457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2774553457 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.3977593511
Short name T42
Test name
Test status
Simulation time 29744733 ps
CPU time 0.77 seconds
Started Mar 14 01:12:37 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215712 kb
Host smart-e0edbdca-9809-4c0e-9554-c8b5870e5803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977593511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3977593511 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.1158319948
Short name T129
Test name
Test status
Simulation time 13091981 ps
CPU time 0.82 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215664 kb
Host smart-e6bef03d-657f-48fc-a037-2d64a539ad61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158319948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.1158319948 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1438459398
Short name T67
Test name
Test status
Simulation time 259142101 ps
CPU time 5.25 seconds
Started Mar 14 01:12:18 PM PDT 24
Finished Mar 14 01:12:24 PM PDT 24
Peak memory 215832 kb
Host smart-f3f27ad6-6907-4110-b813-9619f7a6113d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438459398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1438459
398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.443624873
Short name T27
Test name
Test status
Simulation time 2695987574 ps
CPU time 11.63 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:31 PM PDT 24
Peak memory 215936 kb
Host smart-9cb77376-2c70-4ca6-8eab-800f2948ba61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443624873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.44362487
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1415209714
Short name T110
Test name
Test status
Simulation time 49720657 ps
CPU time 1.12 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 215824 kb
Host smart-717e2712-4f9e-4729-b151-766e680daeb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415209714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1415209
714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.4149786305
Short name T147
Test name
Test status
Simulation time 84135972 ps
CPU time 1.58 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 218960 kb
Host smart-93e226d0-b3d1-4d75-85be-72eb4b94d3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149786305 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.4149786305 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.3893827627
Short name T179
Test name
Test status
Simulation time 177132293 ps
CPU time 1.25 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 215872 kb
Host smart-c18a86dc-b307-4e97-84fc-a44336be7b86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893827627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.3893827627 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.2370987899
Short name T44
Test name
Test status
Simulation time 37372313 ps
CPU time 0.82 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 215708 kb
Host smart-f7252920-0848-4f61-b2ed-679ed5d67410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370987899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2370987899 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2860332060
Short name T52
Test name
Test status
Simulation time 50017458 ps
CPU time 1.12 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 215872 kb
Host smart-725e4c1f-f377-4dde-8bc7-0629d7694e1c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860332060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2860332060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.3391072536
Short name T108
Test name
Test status
Simulation time 17830831 ps
CPU time 0.76 seconds
Started Mar 14 01:12:17 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 215736 kb
Host smart-09b3d6e9-49b7-48ef-953d-4e10f034c937
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391072536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3391072536
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.788504007
Short name T66
Test name
Test status
Simulation time 429405690 ps
CPU time 2.83 seconds
Started Mar 14 01:12:16 PM PDT 24
Finished Mar 14 01:12:19 PM PDT 24
Peak memory 215804 kb
Host smart-b60ca0a1-98b4-4501-aeaf-d5b428dbd7e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788504007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_
outstanding.788504007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2004551973
Short name T85
Test name
Test status
Simulation time 23251595 ps
CPU time 1.03 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:20 PM PDT 24
Peak memory 216100 kb
Host smart-2f948fd1-c5fd-4f21-af93-e5311fae70f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004551973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.2004551973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2759854942
Short name T39
Test name
Test status
Simulation time 59697140 ps
CPU time 2.02 seconds
Started Mar 14 01:12:16 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 218304 kb
Host smart-705e7870-0e17-4159-9090-eff3256d7a8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759854942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.2759854942 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2219202120
Short name T19
Test name
Test status
Simulation time 73212709 ps
CPU time 1.42 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 216016 kb
Host smart-d9e565df-3bf1-47a2-a624-16b498814c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219202120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2219202120 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3753051891
Short name T100
Test name
Test status
Simulation time 200585321 ps
CPU time 2.67 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215884 kb
Host smart-72082c36-9f17-45a5-b9ab-27a24b0b50d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753051891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.37530
51891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.459090711
Short name T168
Test name
Test status
Simulation time 91012081 ps
CPU time 0.81 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215628 kb
Host smart-288b997b-c11e-4274-b706-4423279d6dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459090711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.459090711 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.3513656122
Short name T97
Test name
Test status
Simulation time 16335979 ps
CPU time 0.79 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 215680 kb
Host smart-c33978b7-44d2-471a-b32b-8d090c0e0ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513656122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3513656122 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.4200328793
Short name T87
Test name
Test status
Simulation time 39205102 ps
CPU time 0.82 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215628 kb
Host smart-7eae0829-005a-4bc1-9982-6517afb00413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200328793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.4200328793 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.21704552
Short name T131
Test name
Test status
Simulation time 36964023 ps
CPU time 0.76 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215628 kb
Host smart-ce16582e-2432-43ff-997e-e2e27ddf0c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.21704552 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.312163468
Short name T211
Test name
Test status
Simulation time 37400904 ps
CPU time 0.79 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215600 kb
Host smart-8733d196-cb5d-4a4a-9662-6ec553a38955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312163468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.312163468 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.2112504081
Short name T213
Test name
Test status
Simulation time 13314455 ps
CPU time 0.78 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215596 kb
Host smart-909617a7-141c-4cd9-998c-92574c924ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112504081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2112504081 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.1674242954
Short name T173
Test name
Test status
Simulation time 27985258 ps
CPU time 0.77 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 215720 kb
Host smart-b808f996-a400-4f26-823e-3b5319fad566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674242954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1674242954 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3264214153
Short name T191
Test name
Test status
Simulation time 15291143 ps
CPU time 0.81 seconds
Started Mar 14 01:12:53 PM PDT 24
Finished Mar 14 01:12:55 PM PDT 24
Peak memory 215724 kb
Host smart-45a40cc7-4b80-4d2c-a580-1d7f1ac0e642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264214153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3264214153 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.1222486251
Short name T170
Test name
Test status
Simulation time 54438616 ps
CPU time 0.81 seconds
Started Mar 14 01:12:54 PM PDT 24
Finished Mar 14 01:12:55 PM PDT 24
Peak memory 215728 kb
Host smart-d461b3ac-a979-4b20-b5f7-bb949dd9d800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222486251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1222486251 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.36838588
Short name T47
Test name
Test status
Simulation time 137575217 ps
CPU time 8.07 seconds
Started Mar 14 01:12:18 PM PDT 24
Finished Mar 14 01:12:27 PM PDT 24
Peak memory 215932 kb
Host smart-6ba4c5f1-bc26-46fa-874c-2d56912337a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.36838588
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1953783448
Short name T193
Test name
Test status
Simulation time 1471732116 ps
CPU time 21.64 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:43 PM PDT 24
Peak memory 215884 kb
Host smart-ad3d3852-885c-4f00-a160-1c01a6d1b57c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953783448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1953783
448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.1026319860
Short name T117
Test name
Test status
Simulation time 73254997 ps
CPU time 1.03 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:20 PM PDT 24
Peak memory 215728 kb
Host smart-108df64c-1a30-4739-b0e0-e3166a17cfe5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026319860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.1026319
860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.172347763
Short name T101
Test name
Test status
Simulation time 81490326 ps
CPU time 2.6 seconds
Started Mar 14 01:12:18 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 220908 kb
Host smart-c7318c7c-d1b6-4de0-aba7-c4f2edddd76f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172347763 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.172347763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.3960464984
Short name T96
Test name
Test status
Simulation time 45334753 ps
CPU time 0.94 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215620 kb
Host smart-4f0ae340-ee91-42d9-bc3d-37b1be242faa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960464984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3960464984 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.3640645772
Short name T210
Test name
Test status
Simulation time 73188903 ps
CPU time 0.81 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 215676 kb
Host smart-d145e726-c2b2-4fc0-b878-a9c28afefcd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640645772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3640645772 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2366912208
Short name T50
Test name
Test status
Simulation time 20169195 ps
CPU time 1.29 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215828 kb
Host smart-d8c0df3d-b4e5-4a15-a80e-2e7826b946ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366912208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2366912208 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1864834744
Short name T2
Test name
Test status
Simulation time 31304326 ps
CPU time 0.75 seconds
Started Mar 14 01:12:18 PM PDT 24
Finished Mar 14 01:12:19 PM PDT 24
Peak memory 215764 kb
Host smart-17512286-bd3c-475d-bb58-2701b8c6de41
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864834744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1864834744
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1850890008
Short name T208
Test name
Test status
Simulation time 224371212 ps
CPU time 2.62 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:24 PM PDT 24
Peak memory 215856 kb
Host smart-a364adfb-6fd9-484f-8812-cd73bca4f58a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850890008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1850890008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2339665779
Short name T84
Test name
Test status
Simulation time 65479765 ps
CPU time 1.16 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:21 PM PDT 24
Peak memory 216652 kb
Host smart-e6e2cbd9-5a61-4a7e-917e-0c3fa8957fc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339665779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.2339665779 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.3031038712
Short name T194
Test name
Test status
Simulation time 100276092 ps
CPU time 1.92 seconds
Started Mar 14 01:12:16 PM PDT 24
Finished Mar 14 01:12:18 PM PDT 24
Peak memory 216004 kb
Host smart-c0a55239-799a-4ef3-ad34-9e5977b57d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031038712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3031038712 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2226415422
Short name T71
Test name
Test status
Simulation time 372978046 ps
CPU time 4.26 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:23 PM PDT 24
Peak memory 215932 kb
Host smart-0b06bd11-bdcf-4a93-bbc4-5989ba4cf660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226415422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.22264
15422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.4243871066
Short name T102
Test name
Test status
Simulation time 11745863 ps
CPU time 0.81 seconds
Started Mar 14 01:13:00 PM PDT 24
Finished Mar 14 01:13:01 PM PDT 24
Peak memory 215568 kb
Host smart-5bf36a8f-a042-4ddf-986c-4344d5e9d2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243871066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.4243871066 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.3733382433
Short name T162
Test name
Test status
Simulation time 27159580 ps
CPU time 0.79 seconds
Started Mar 14 01:12:54 PM PDT 24
Finished Mar 14 01:12:55 PM PDT 24
Peak memory 215676 kb
Host smart-7225f6d6-eac8-4422-a637-071fe2c11f0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733382433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3733382433 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1710776990
Short name T185
Test name
Test status
Simulation time 40934769 ps
CPU time 0.83 seconds
Started Mar 14 01:12:46 PM PDT 24
Finished Mar 14 01:12:47 PM PDT 24
Peak memory 215964 kb
Host smart-8c240dd3-a870-44d8-a59d-9b35abb8cfb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710776990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1710776990 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.1465188105
Short name T35
Test name
Test status
Simulation time 18492441 ps
CPU time 0.88 seconds
Started Mar 14 01:12:53 PM PDT 24
Finished Mar 14 01:12:54 PM PDT 24
Peak memory 215724 kb
Host smart-00ada409-f729-46d2-a460-d73d80ecba69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465188105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1465188105 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.380825254
Short name T158
Test name
Test status
Simulation time 40822214 ps
CPU time 0.88 seconds
Started Mar 14 01:12:53 PM PDT 24
Finished Mar 14 01:12:55 PM PDT 24
Peak memory 215724 kb
Host smart-563ad68e-a171-49a0-973f-132ea907129e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380825254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.380825254 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2789580189
Short name T200
Test name
Test status
Simulation time 37768700 ps
CPU time 0.83 seconds
Started Mar 14 01:12:47 PM PDT 24
Finished Mar 14 01:12:48 PM PDT 24
Peak memory 215964 kb
Host smart-d0875c9b-311a-4dfa-9d1d-625dbd29858e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789580189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2789580189 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.4025408976
Short name T125
Test name
Test status
Simulation time 54615528 ps
CPU time 0.79 seconds
Started Mar 14 01:12:50 PM PDT 24
Finished Mar 14 01:12:51 PM PDT 24
Peak memory 215724 kb
Host smart-2366a079-f253-48a0-822e-94af0da76cb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025408976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.4025408976 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1917602153
Short name T36
Test name
Test status
Simulation time 146675266 ps
CPU time 0.83 seconds
Started Mar 14 01:12:54 PM PDT 24
Finished Mar 14 01:12:55 PM PDT 24
Peak memory 215668 kb
Host smart-eea48fd1-78f8-4d71-a521-5cb38c23c14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917602153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1917602153 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2444723217
Short name T169
Test name
Test status
Simulation time 34825291 ps
CPU time 0.77 seconds
Started Mar 14 01:13:00 PM PDT 24
Finished Mar 14 01:13:01 PM PDT 24
Peak memory 215532 kb
Host smart-61921ffd-001e-4229-8b8b-a27b78357521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444723217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2444723217 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3320720178
Short name T122
Test name
Test status
Simulation time 16130934 ps
CPU time 0.81 seconds
Started Mar 14 01:12:45 PM PDT 24
Finished Mar 14 01:12:46 PM PDT 24
Peak memory 215640 kb
Host smart-fc98b6fb-0f95-44b1-90d1-fcc8c314a4eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320720178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3320720178 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2649784098
Short name T141
Test name
Test status
Simulation time 778515264 ps
CPU time 2.27 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:24 PM PDT 24
Peak memory 220612 kb
Host smart-7b0b0471-7fc5-4728-970c-5ec285e56f56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649784098 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.2649784098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.1087058719
Short name T156
Test name
Test status
Simulation time 30809896 ps
CPU time 0.96 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215676 kb
Host smart-a14d5e33-2cf6-486c-9f5e-12f733d5ff81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087058719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.1087058719 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.2818271105
Short name T29
Test name
Test status
Simulation time 13014845 ps
CPU time 0.8 seconds
Started Mar 14 01:12:21 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215700 kb
Host smart-e4d0b120-110e-4a23-a93f-5282b9049d86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818271105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2818271105 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.475467843
Short name T83
Test name
Test status
Simulation time 41931788 ps
CPU time 2.18 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215908 kb
Host smart-407b39f2-2dd1-4c80-b1d4-b2aae3334873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475467843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_
outstanding.475467843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.576125798
Short name T81
Test name
Test status
Simulation time 57790584 ps
CPU time 1.39 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 217412 kb
Host smart-16978544-c237-47c2-9dfa-5c53289c7a38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576125798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.576125798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3520918488
Short name T207
Test name
Test status
Simulation time 85584341 ps
CPU time 2.47 seconds
Started Mar 14 01:12:19 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 218920 kb
Host smart-f46b666d-c647-4544-8aee-7d044cafd71c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520918488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.3520918488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.3872791231
Short name T153
Test name
Test status
Simulation time 351893421 ps
CPU time 2.62 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:22 PM PDT 24
Peak memory 215980 kb
Host smart-1a6674d7-06da-4318-a556-8243717f79e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872791231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3872791231 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2744365224
Short name T165
Test name
Test status
Simulation time 532995260 ps
CPU time 3.21 seconds
Started Mar 14 01:12:20 PM PDT 24
Finished Mar 14 01:12:23 PM PDT 24
Peak memory 215820 kb
Host smart-403ff8eb-690b-4563-8e8a-b5ac832366c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744365224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.27443
65224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2139742795
Short name T187
Test name
Test status
Simulation time 81851063 ps
CPU time 1.75 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 220152 kb
Host smart-67e8f6e7-4537-4e1a-8715-a5f22c0b1f96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139742795 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2139742795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.628627598
Short name T92
Test name
Test status
Simulation time 20177221 ps
CPU time 0.98 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215812 kb
Host smart-8144b062-e734-4f63-a87a-00fb5fbe4671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628627598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.628627598 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.2587529271
Short name T12
Test name
Test status
Simulation time 49627723 ps
CPU time 0.79 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 215600 kb
Host smart-c01833e8-ba33-40bc-8ffa-bd3bfb69d27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587529271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2587529271 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.519062221
Short name T121
Test name
Test status
Simulation time 95885232 ps
CPU time 1.6 seconds
Started Mar 14 01:12:30 PM PDT 24
Finished Mar 14 01:12:32 PM PDT 24
Peak memory 215912 kb
Host smart-80507033-035a-4d1e-91bc-0ea854801d41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519062221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_
outstanding.519062221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1186175978
Short name T178
Test name
Test status
Simulation time 29445512 ps
CPU time 1.15 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 216508 kb
Host smart-af1e8529-2769-4ad0-ad32-e49914cdce69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186175978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1186175978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1491535622
Short name T176
Test name
Test status
Simulation time 217260035 ps
CPU time 1.67 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 219232 kb
Host smart-faea291a-1384-440e-802b-13c13c4586c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491535622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1491535622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2909307769
Short name T205
Test name
Test status
Simulation time 235114079 ps
CPU time 3.65 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:37 PM PDT 24
Peak memory 216060 kb
Host smart-5432e4fb-64d7-42f4-ae04-219baeea797e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909307769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2909307769 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4012042650
Short name T8
Test name
Test status
Simulation time 187417137 ps
CPU time 4.31 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 215896 kb
Host smart-1f17fd6d-2bca-4ee3-bd8a-e73af7d2b986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012042650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.40120
42650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3592098531
Short name T99
Test name
Test status
Simulation time 25535120 ps
CPU time 1.74 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:40 PM PDT 24
Peak memory 220212 kb
Host smart-5ffb416e-53ce-4a7c-a396-4aa7b6a8bb90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592098531 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3592098531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.2543702075
Short name T106
Test name
Test status
Simulation time 17370557 ps
CPU time 0.93 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215716 kb
Host smart-d79b6193-78ff-45bd-bcbb-ced006cd7334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543702075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2543702075 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1746109223
Short name T133
Test name
Test status
Simulation time 23320803 ps
CPU time 0.78 seconds
Started Mar 14 01:12:31 PM PDT 24
Finished Mar 14 01:12:32 PM PDT 24
Peak memory 215688 kb
Host smart-4aa5d244-7d3f-4875-9d82-2ce78a8d4665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746109223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1746109223 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3545698958
Short name T120
Test name
Test status
Simulation time 66086045 ps
CPU time 1.67 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215896 kb
Host smart-d714f95e-7d32-4893-b26c-a4069987626a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545698958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.3545698958 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.114938408
Short name T160
Test name
Test status
Simulation time 25022318 ps
CPU time 0.99 seconds
Started Mar 14 01:12:29 PM PDT 24
Finished Mar 14 01:12:30 PM PDT 24
Peak memory 215748 kb
Host smart-42fe3eaf-5e51-4b09-b3fc-814a246affc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114938408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_e
rrors.114938408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2573397642
Short name T175
Test name
Test status
Simulation time 92793430 ps
CPU time 2.41 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 219576 kb
Host smart-de23ca1a-3206-4ab0-839d-8bd3e39af46a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573397642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.2573397642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.3111905181
Short name T21
Test name
Test status
Simulation time 1715361032 ps
CPU time 3.35 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 215948 kb
Host smart-8d5dfa26-d29a-4e32-92e7-4222f166e24b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111905181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3111905181 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1033766620
Short name T77
Test name
Test status
Simulation time 179568998 ps
CPU time 2.84 seconds
Started Mar 14 01:12:31 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 215936 kb
Host smart-458e8078-66fe-407a-917e-464b81946d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033766620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.10337
66620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1820219130
Short name T13
Test name
Test status
Simulation time 36605801 ps
CPU time 2.48 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:35 PM PDT 24
Peak memory 221400 kb
Host smart-afd33259-2e48-4b47-a75d-952c933409f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820219130 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1820219130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1114757065
Short name T25
Test name
Test status
Simulation time 120900744 ps
CPU time 1.15 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:36 PM PDT 24
Peak memory 215864 kb
Host smart-45c11ed5-5886-4dad-ac57-21f6ef4c598e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114757065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1114757065 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3370496353
Short name T104
Test name
Test status
Simulation time 44728526 ps
CPU time 0.79 seconds
Started Mar 14 01:12:32 PM PDT 24
Finished Mar 14 01:12:33 PM PDT 24
Peak memory 215644 kb
Host smart-52df7de1-8a1b-4d71-8050-66fce2082294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370496353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3370496353 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.885167498
Short name T212
Test name
Test status
Simulation time 177155555 ps
CPU time 2.46 seconds
Started Mar 14 01:12:38 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215916 kb
Host smart-5c5a3c4a-4ad8-4935-8973-b10dcb707ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885167498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_
outstanding.885167498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.117600355
Short name T182
Test name
Test status
Simulation time 54529731 ps
CPU time 0.88 seconds
Started Mar 14 01:12:34 PM PDT 24
Finished Mar 14 01:12:35 PM PDT 24
Peak memory 215752 kb
Host smart-ded0fcb7-42b0-4927-b057-ba22808aef91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117600355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e
rrors.117600355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3064775316
Short name T46
Test name
Test status
Simulation time 132844617 ps
CPU time 1.87 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:42 PM PDT 24
Peak memory 216372 kb
Host smart-80610d62-8a1b-4f0e-8897-996b1c6b2d9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064775316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3064775316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3616134145
Short name T22
Test name
Test status
Simulation time 127878707 ps
CPU time 2.97 seconds
Started Mar 14 01:12:36 PM PDT 24
Finished Mar 14 01:12:39 PM PDT 24
Peak memory 216016 kb
Host smart-3920537a-adbc-4dbc-b438-ef07a7f1bbc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616134145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3616134145 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1217266215
Short name T186
Test name
Test status
Simulation time 143604546 ps
CPU time 1.57 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 218972 kb
Host smart-5ee87570-3e74-4edf-816c-1fc651b3d4c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217266215 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.1217266215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.3140257985
Short name T124
Test name
Test status
Simulation time 24071370 ps
CPU time 1.09 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 215808 kb
Host smart-fda2b03a-67ed-4144-9d64-653df4a7c008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140257985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3140257985 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.4036597953
Short name T167
Test name
Test status
Simulation time 31799040 ps
CPU time 0.77 seconds
Started Mar 14 01:12:40 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 215672 kb
Host smart-810e7540-5175-417b-b7c2-4421f78ed525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036597953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.4036597953 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4152888243
Short name T30
Test name
Test status
Simulation time 92185894 ps
CPU time 1.54 seconds
Started Mar 14 01:12:31 PM PDT 24
Finished Mar 14 01:12:33 PM PDT 24
Peak memory 215904 kb
Host smart-c4f8d65a-4c5d-42ff-b058-6bdc2d00d9cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152888243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.4152888243 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2439046530
Short name T41
Test name
Test status
Simulation time 36386992 ps
CPU time 1.09 seconds
Started Mar 14 01:12:33 PM PDT 24
Finished Mar 14 01:12:34 PM PDT 24
Peak memory 216300 kb
Host smart-49cfad94-a524-4c42-8b2d-6e5beed6053c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439046530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.2439046530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3459572516
Short name T61
Test name
Test status
Simulation time 277422421 ps
CPU time 2.8 seconds
Started Mar 14 01:12:39 PM PDT 24
Finished Mar 14 01:12:41 PM PDT 24
Peak memory 216000 kb
Host smart-fe2c9b61-8681-46ab-8246-23e83696acce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459572516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3459572516 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1049116684
Short name T69
Test name
Test status
Simulation time 119842029 ps
CPU time 2.94 seconds
Started Mar 14 01:12:35 PM PDT 24
Finished Mar 14 01:12:38 PM PDT 24
Peak memory 215988 kb
Host smart-626c8f95-0a26-42a6-bdec-2feaab32bf93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049116684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.10491
16684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest
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