Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	305	1			T11	7		T12	5		T35	8
all_pins[1]	305	1			T11	7		T12	5		T35	8
all_pins[2]	305	1			T11	7		T12	5		T35	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	760	1			T11	15		T12	13		T35	20
values[0x1]	155	1			T11	6		T12	2		T35	4
transitions[0x0=>0x1]	117	1			T11	4		T12	2		T35	3
transitions[0x1=>0x0]	122	1			T11	5		T12	2		T35	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	252	1			T11	7		T12	4		T35	8
all_pins[0]	values[0x1]	53	1			T12	1		T23	2		T28	3
all_pins[0]	transitions[0x0=>0x1]	44	1			T12	1		T23	1		T28	2
all_pins[0]	transitions[0x1=>0x0]	44	1			T11	4		T12	1		T35	2
all_pins[1]	values[0x0]	252	1			T11	3		T12	4		T35	6
all_pins[1]	values[0x1]	53	1			T11	4		T12	1		T35	2
all_pins[1]	transitions[0x0=>0x1]	41	1			T11	3		T12	1		T35	1
all_pins[1]	transitions[0x1=>0x0]	37	1			T11	1		T35	1		T36	1
all_pins[2]	values[0x0]	256	1			T11	5		T12	5		T35	6
all_pins[2]	values[0x1]	49	1			T11	2		T35	2		T36	1
all_pins[2]	transitions[0x0=>0x1]	32	1			T11	1		T35	2		T36	1
all_pins[2]	transitions[0x1=>0x0]	41	1			T12	1		T23	1		T28	3