Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 254 1 T11 7 T12 4 T35 7
all_values[1] 254 1 T11 7 T12 4 T35 7
all_values[2] 254 1 T11 7 T12 4 T35 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 416 1 T11 12 T12 9 T35 14
auto[1] 346 1 T11 9 T12 3 T35 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 393 1 T11 9 T12 3 T35 7
auto[1] 369 1 T11 12 T12 9 T35 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 472 1 T11 11 T12 5 T35 9
auto[1] 290 1 T11 10 T12 7 T35 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 50 1 T11 2 T12 1 T35 2
all_values[0] auto[0] auto[0] auto[1] 14 1 T11 1 T35 1 T23 1
all_values[0] auto[0] auto[1] auto[0] 69 1 T11 2 T12 1 T36 5
all_values[0] auto[0] auto[1] auto[1] 21 1 T23 1 T28 1 T29 1
all_values[0] auto[1] auto[0] auto[1] 56 1 T11 1 T12 1 T35 4
all_values[0] auto[1] auto[1] auto[1] 44 1 T11 1 T12 1 T23 2
all_values[1] auto[0] auto[0] auto[0] 85 1 T11 2 T12 1 T35 1
all_values[1] auto[0] auto[1] auto[0] 77 1 T11 1 T35 1 T36 3
all_values[1] auto[1] auto[0] auto[1] 52 1 T11 2 T12 2 T35 2
all_values[1] auto[1] auto[1] auto[1] 40 1 T11 2 T12 1 T35 3
all_values[2] auto[0] auto[0] auto[0] 73 1 T35 1 T36 2 T28 1
all_values[2] auto[0] auto[0] auto[1] 26 1 T12 2 T35 1 T36 1
all_values[2] auto[0] auto[1] auto[0] 39 1 T11 2 T35 2 T36 2
all_values[2] auto[0] auto[1] auto[1] 18 1 T11 1 T44 1 T45 1
all_values[2] auto[1] auto[0] auto[1] 60 1 T11 4 T12 2 T35 2
all_values[2] auto[1] auto[1] auto[1] 38 1 T35 1 T36 2 T23 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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