Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261183020	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

187496306

1

T1

177334

T2

172

T3

792840

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232288626	1			T1	233005		T2	90		T3	102964
values[0x0]	104000021	1			T1	109663		T2	45		T3	445082
values[0x1]	112390679	1			T1	119058		T2	49		T3	480505

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202899220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

245780106

1

T1

240293

T2

176

T3

104906

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3825392	1			T1	1565		T3	7469		T13	601
valid_sources[0x01]	1530065	1			T1	1620		T2	2		T3	7852
valid_sources[0x02]	2325440	1			T1	1795		T3	7597		T7	2
valid_sources[0x03]	1405725	1			T1	1888		T2	4		T3	7640
valid_sources[0x04]	1406439	1			T1	1608		T3	7546		T7	10
valid_sources[0x05]	1415147	1			T1	1647		T3	7725		T13	675
valid_sources[0x06]	1410936	1			T1	1905		T3	7656		T7	4
valid_sources[0x07]	1408235	1			T1	1893		T3	7519		T7	18
valid_sources[0x08]	3404649	1			T1	1622		T3	7523		T7	3
valid_sources[0x09]	1405762	1			T1	2016		T3	7539		T7	10
valid_sources[0x0a]	1407748	1			T1	1646		T3	7545		T13	602
valid_sources[0x0b]	2301507	1			T1	1622		T3	7679		T7	11
valid_sources[0x0c]	1404949	1			T1	1584		T2	5		T3	7796
valid_sources[0x0d]	1402618	1			T1	1760		T3	7850		T7	2
valid_sources[0x0e]	1403633	1			T1	1595		T3	7477		T7	10
valid_sources[0x0f]	1412450	1			T1	1880		T2	1		T3	7751
valid_sources[0x10]	1406217	1			T1	1916		T3	7835		T7	10
valid_sources[0x11]	3334419	1			T1	1702		T3	7688		T13	653
valid_sources[0x12]	1618451	1			T1	1935		T3	7847		T7	19
valid_sources[0x13]	1409504	1			T1	1977		T3	7551		T7	8
valid_sources[0x14]	1650311	1			T1	1841		T3	7724		T7	5
valid_sources[0x15]	1404686	1			T1	1764		T3	7530		T7	8
valid_sources[0x16]	1431902	1			T1	1957		T3	7643		T13	570
valid_sources[0x17]	1409052	1			T1	1931		T3	7678		T7	16
valid_sources[0x18]	1868292	1			T1	1769		T3	7618		T13	707
valid_sources[0x19]	1400580	1			T1	1769		T3	7912		T7	12
valid_sources[0x1a]	1406672	1			T1	1630		T3	7493		T7	12
valid_sources[0x1b]	2315964	1			T1	2056		T3	7579		T7	8
valid_sources[0x1c]	1399994	1			T1	1989		T3	7783		T13	692
valid_sources[0x1d]	1400491	1			T1	1820		T3	7668		T7	10
valid_sources[0x1e]	1400133	1			T1	1606		T2	4		T3	7753
valid_sources[0x1f]	1504232	1			T1	1864		T3	7398		T7	4
valid_sources[0x20]	3756374	1			T1	1923		T3	7741		T7	2
valid_sources[0x21]	1412936	1			T1	2044		T3	7646		T7	1
valid_sources[0x22]	1402300	1			T1	1859		T2	3		T3	7558
valid_sources[0x23]	1400205	1			T1	2123		T3	7546		T7	12
valid_sources[0x24]	1856534	1			T1	1760		T3	7670		T7	20
valid_sources[0x25]	1403850	1			T1	1750		T3	7679		T13	672
valid_sources[0x26]	2077623	1			T1	1795		T3	7689		T7	10
valid_sources[0x27]	1393401	1			T1	1731		T3	7876		T7	12
valid_sources[0x28]	2311566	1			T1	1829		T3	7778		T13	612
valid_sources[0x29]	3511530	1			T1	1660		T3	7378		T13	780
valid_sources[0x2a]	3408827	1			T1	1706		T3	7214		T7	5
valid_sources[0x2b]	1442679	1			T1	1571		T3	7454		T7	21
valid_sources[0x2c]	2037015	1			T1	1848		T3	7470		T13	605
valid_sources[0x2d]	1434850	1			T1	2027		T3	7433		T13	595
valid_sources[0x2e]	1410087	1			T1	1940		T3	7604		T13	667
valid_sources[0x2f]	1396869	1			T1	1888		T3	7575		T7	13
valid_sources[0x30]	1401791	1			T1	1796		T3	7597		T7	8
valid_sources[0x31]	1408859	1			T1	1372		T3	7556		T13	712
valid_sources[0x32]	1410567	1			T1	1771		T3	7657		T7	1
valid_sources[0x33]	1403313	1			T1	1697		T3	7777		T13	584
valid_sources[0x34]	1409901	1			T1	1551		T3	7345		T7	3
valid_sources[0x35]	1403810	1			T1	1654		T3	7572		T7	12
valid_sources[0x36]	1399626	1			T1	1989		T3	7544		T7	1
valid_sources[0x37]	1562542	1			T1	1820		T3	7510		T7	2
valid_sources[0x38]	1405756	1			T1	2083		T3	7704		T7	3
valid_sources[0x39]	1407526	1			T1	1820		T3	7588		T13	555
valid_sources[0x3a]	1409516	1			T1	1651		T3	7471		T7	9
valid_sources[0x3b]	3717129	1			T1	1803		T3	7617		T7	15
valid_sources[0x3c]	1398160	1			T1	1824		T3	7753		T7	18
valid_sources[0x3d]	2057267	1			T1	1819		T3	7549		T7	9
valid_sources[0x3e]	1398755	1			T1	2012		T3	7691		T7	21
valid_sources[0x3f]	1406019	1			T1	2100		T3	7700		T7	2
valid_sources[0x40]	2079870	1			T1	1755		T2	4		T3	7918
valid_sources[0x41]	2056461	1			T1	2045		T3	7728		T7	2
valid_sources[0x42]	2361248	1			T1	2060		T2	7		T3	7528
valid_sources[0x43]	1397256	1			T1	1656		T3	7640		T7	15
valid_sources[0x44]	2272249	1			T1	1634		T3	7717		T7	3
valid_sources[0x45]	1409088	1			T1	1950		T3	7669		T7	1
valid_sources[0x46]	2268639	1			T1	1870		T3	7426		T7	4
valid_sources[0x47]	1464310	1			T1	1638		T3	7700		T7	6
valid_sources[0x48]	1460927	1			T1	1838		T3	7602		T7	1
valid_sources[0x49]	1402534	1			T1	1590		T3	7431		T7	15
valid_sources[0x4a]	2266861	1			T1	1836		T3	7735		T7	8
valid_sources[0x4b]	1401690	1			T1	1526		T3	7488		T7	7
valid_sources[0x4c]	1400978	1			T1	1867		T3	7848		T7	2
valid_sources[0x4d]	1405895	1			T1	1812		T2	3		T3	7518
valid_sources[0x4e]	2056413	1			T1	1951		T3	7509		T7	9
valid_sources[0x4f]	2355863	1			T1	1961		T3	7569		T7	9
valid_sources[0x50]	1448696	1			T1	1695		T3	7643		T13	662
valid_sources[0x51]	1401875	1			T1	1544		T3	7379		T7	14
valid_sources[0x52]	1492619	1			T1	1649		T3	7638		T13	684
valid_sources[0x53]	1508597	1			T1	1866		T3	7680		T7	4
valid_sources[0x54]	1394916	1			T1	2030		T3	7703		T7	30
valid_sources[0x55]	1415158	1			T1	1860		T2	4		T3	7521
valid_sources[0x56]	2429793	1			T1	1901		T2	3		T3	7795
valid_sources[0x57]	1404429	1			T1	1716		T2	2		T3	7726
valid_sources[0x58]	1394498	1			T1	1695		T2	5		T3	7763
valid_sources[0x59]	1407990	1			T1	1775		T3	7744		T7	10
valid_sources[0x5a]	3738563	1			T1	2026		T2	1		T3	7746
valid_sources[0x5b]	3371774	1			T1	1689		T3	7697		T7	14
valid_sources[0x5c]	1398921	1			T1	1860		T3	7547		T7	3
valid_sources[0x5d]	1449771	1			T1	1582		T3	7711		T13	591
valid_sources[0x5e]	2924311	1			T1	1980		T3	7368		T7	1
valid_sources[0x5f]	2238828	1			T1	1558		T3	7777		T7	13
valid_sources[0x60]	3353886	1			T1	1973		T2	10		T3	7738
valid_sources[0x61]	1404506	1			T1	1687		T3	7460		T13	647
valid_sources[0x62]	1403995	1			T1	1815		T3	7833		T7	9
valid_sources[0x63]	1409970	1			T1	1951		T3	7668		T13	584
valid_sources[0x64]	1653476	1			T1	1683		T3	7659		T13	654
valid_sources[0x65]	1412125	1			T1	1916		T2	13		T3	7682
valid_sources[0x66]	2507136	1			T1	1767		T3	7670		T13	490
valid_sources[0x67]	1405217	1			T1	1706		T3	7751		T7	3
valid_sources[0x68]	2079014	1			T1	1827		T3	7746		T13	585
valid_sources[0x69]	1416587	1			T1	1863		T3	7680		T7	9
valid_sources[0x6a]	1857099	1			T1	1779		T3	7727		T7	10
valid_sources[0x6b]	1444159	1			T1	1560		T3	7499		T7	5
valid_sources[0x6c]	1724212	1			T1	1767		T3	7655		T7	12
valid_sources[0x6d]	1405553	1			T1	1770		T2	12		T3	7725
valid_sources[0x6e]	1399914	1			T1	1554		T2	3		T3	7684
valid_sources[0x6f]	1437657	1			T1	1840		T3	7710		T13	575
valid_sources[0x70]	1449238	1			T1	1638		T2	2		T3	7592
valid_sources[0x71]	1400220	1			T1	1923		T3	7575		T7	24
valid_sources[0x72]	1409985	1			T1	1807		T3	7752		T7	8
valid_sources[0x73]	1402735	1			T1	1740		T3	7514		T13	699
valid_sources[0x74]	1399741	1			T1	2085		T3	7570		T13	510
valid_sources[0x75]	1406364	1			T1	1662		T3	7804		T7	10
valid_sources[0x76]	1537794	1			T1	1610		T3	7565		T13	666
valid_sources[0x77]	1412903	1			T1	1478		T3	7667		T7	39
valid_sources[0x78]	2467252	1			T1	1827		T3	7691		T7	19
valid_sources[0x79]	1400597	1			T1	1733		T3	7759		T7	3
valid_sources[0x7a]	1403593	1			T1	1705		T3	7675		T13	722
valid_sources[0x7b]	1410132	1			T1	1924		T3	7617		T13	828
valid_sources[0x7c]	1401077	1			T1	1633		T2	3		T3	7428
valid_sources[0x7d]	1404445	1			T1	1922		T3	7484		T7	4
valid_sources[0x7e]	3709167	1			T1	2121		T3	7528		T7	1
valid_sources[0x7f]	1499361	1			T1	1850		T3	7622		T7	15
valid_sources[0x80]	2246728	1			T1	1622		T3	7513		T13	603

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71956881

1

T1

64498

T2

85

T3

321066

values[0x0]

all_enables

biggest_size

61988369

1

T1

61302

T2

43

T3

255132

values[0x1]

all_enables

biggest_size

53551056

1

T1

51534

T2

44

T3

216642