Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263771208

1

T1

284392

T2

12

T3

116239

full_word

187658330

1

T1

177334

T2

172

T3

792840

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451429238	1			T1	461726		T2	184		T3	195523
auto[TlIntgErrCmd]	94	1			T132	5		T133	7		T134	3
auto[TlIntgErrData]	106	1			T132	10		T133	8		T134	4
auto[TlIntgErrBoth]	100	1			T132	5		T133	5		T134	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232788734

1

T1

233005

T2

90

T3

102964

auto[1]

218640804

1

T1

228721

T2

94

T3

925587

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160791141	1			T1	168507		T2	5		T3	708577
auto[TlIntgErrNone]	partial	auto[1]	102979791	1			T1	115885		T2	7		T3	453813
auto[TlIntgErrNone]	full_word	auto[0]	71997460	1			T1	64498		T2	85		T3	321066
auto[TlIntgErrNone]	full_word	auto[1]	115660846	1			T1	112836		T2	87		T3	471774
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T132	1		T133	3		T134	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T132	2		T133	2		T134	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T132	1		T184	1		T187	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T132	1		T133	2		T188	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T132	4		T133	3		T134	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T132	6		T133	2		T134	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T133	2		T189	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T133	1		T189	1		T190	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T132	3		T165	2		T189	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T132	2		T133	4		T134	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T191	1		T192	1		T193	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T133	1		T185	1		T188	2