Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	593097	0	0
entropy_period_rd_A	2147483647	1035	0	0
intr_enable_rd_A	2147483647	1420	0	0
prefix_0_rd_A	2147483647	759	0	0
prefix_10_rd_A	2147483647	714	0	0
prefix_1_rd_A	2147483647	677	0	0
prefix_2_rd_A	2147483647	716	0	0
prefix_3_rd_A	2147483647	803	0	0
prefix_4_rd_A	2147483647	812	0	0
prefix_5_rd_A	2147483647	761	0	0
prefix_6_rd_A	2147483647	812	0	0
prefix_7_rd_A	2147483647	738	0	0
prefix_8_rd_A	2147483647	768	0	0
prefix_9_rd_A	2147483647	842	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	593097	0	0
T12	284818	0	0	0
T38	956444	0	0	0
T39	0	18467	0	0
T48	55185	0	0	0
T66	233925	21012	0	0
T67	0	32983	0	0
T139	0	34842	0	0
T140	0	15214	0	0
T141	0	68892	0	0
T142	0	16462	0	0
T143	0	124178	0	0
T144	0	22705	0	0
T145	0	49622	0	0
T146	19670	0	0	0
T147	22879	0	0	0
T148	148623	0	0	0
T149	622228	0	0	0
T150	52762	0	0	0
T151	603942	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1035	0	0
T97	12943	88	0	0
T101	3641	8	0	0
T133	24150	144	0	0
T160	5837	22	0	0
T161	3014	14	0	0
T162	10180	36	0	0
T163	11433	22	0	0
T164	10713	29	0	0
T165	11090	33	0	0
T166	10924	38	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1420	0	0
T97	12943	89	0	0
T133	24150	146	0	0
T137	1445	9	0	0
T161	3014	2	0	0
T162	10180	29	0	0
T163	11433	39	0	0
T164	10713	28	0	0
T167	1497	16	0	0
T168	1011	3	0	0
T169	5076	17	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	759	0	0
T97	12943	56	0	0
T101	3641	7	0	0
T133	24150	76	0	0
T161	3014	15	0	0
T162	10180	13	0	0
T163	11433	56	0	0
T164	10713	43	0	0
T165	11090	21	0	0
T166	10924	17	0	0
T169	5076	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	714	0	0
T97	12943	61	0	0
T101	3641	6	0	0
T133	24150	75	0	0
T160	5837	37	0	0
T161	3014	1	0	0
T162	10180	7	0	0
T163	11433	30	0	0
T164	10713	33	0	0
T165	11090	18	0	0
T169	5076	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	677	0	0
T97	12943	65	0	0
T101	3641	15	0	0
T133	24150	89	0	0
T160	5837	10	0	0
T161	3014	4	0	0
T162	10180	2	0	0
T163	11433	52	0	0
T164	10713	43	0	0
T165	11090	14	0	0
T169	5076	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	716	0	0
T97	12943	41	0	0
T101	3641	5	0	0
T133	24150	64	0	0
T160	5837	33	0	0
T161	3014	6	0	0
T162	10180	22	0	0
T163	11433	41	0	0
T164	10713	33	0	0
T165	11090	37	0	0
T169	5076	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	803	0	0
T97	12943	55	0	0
T101	3641	8	0	0
T133	24150	95	0	0
T160	5837	25	0	0
T161	3014	3	0	0
T162	10180	23	0	0
T163	11433	47	0	0
T164	10713	16	0	0
T165	11090	29	0	0
T166	10924	23	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	812	0	0
T97	12943	77	0	0
T101	3641	16	0	0
T133	24150	79	0	0
T160	5837	29	0	0
T161	3014	6	0	0
T162	10180	6	0	0
T163	11433	50	0	0
T164	10713	26	0	0
T165	11090	31	0	0
T169	5076	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	761	0	0
T97	12943	62	0	0
T101	3641	5	0	0
T133	24150	90	0	0
T160	5837	23	0	0
T161	3014	8	0	0
T162	10180	29	0	0
T163	11433	40	0	0
T164	10713	10	0	0
T165	11090	26	0	0
T169	5076	1	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	812	0	0
T97	12943	57	0	0
T101	3641	4	0	0
T133	24150	62	0	0
T160	5837	22	0	0
T161	3014	4	0	0
T162	10180	53	0	0
T163	11433	34	0	0
T164	10713	24	0	0
T165	11090	24	0	0
T169	5076	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	738	0	0
T97	12943	45	0	0
T101	3641	2	0	0
T133	24150	67	0	0
T160	5837	30	0	0
T161	3014	16	0	0
T162	10180	13	0	0
T163	11433	27	0	0
T164	10713	40	0	0
T165	11090	23	0	0
T169	5076	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	768	0	0
T97	12943	45	0	0
T101	3641	17	0	0
T133	24150	77	0	0
T160	5837	28	0	0
T161	3014	5	0	0
T162	10180	36	0	0
T163	11433	36	0	0
T164	10713	13	0	0
T165	11090	11	0	0
T169	5076	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	842	0	0
T97	12943	58	0	0
T133	24150	87	0	0
T160	5837	26	0	0
T161	3014	12	0	0
T162	10180	24	0	0
T163	11433	59	0	0
T164	10713	20	0	0
T165	11090	28	0	0
T166	10924	42	0	0
T169	5076	1	0	0