Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177843 |
1 |
|
|
T7 |
105 |
|
T8 |
627 |
|
T16 |
23 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91854 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63795 |
1 |
|
|
T7 |
104 |
|
T8 |
618 |
|
T16 |
22 |
seven_bytes |
3224 |
1 |
|
|
T9 |
28 |
|
T58 |
29 |
|
T60 |
53 |
six_bytes |
3181 |
1 |
|
|
T9 |
25 |
|
T58 |
30 |
|
T60 |
51 |
five_bytes |
3149 |
1 |
|
|
T9 |
25 |
|
T58 |
21 |
|
T60 |
50 |
four_bytes |
3201 |
1 |
|
|
T9 |
26 |
|
T58 |
28 |
|
T60 |
48 |
three_bytes |
3155 |
1 |
|
|
T9 |
32 |
|
T58 |
40 |
|
T60 |
65 |
two_bytes |
3068 |
1 |
|
|
T9 |
20 |
|
T58 |
32 |
|
T60 |
63 |
one_byte |
3216 |
1 |
|
|
T9 |
26 |
|
T58 |
37 |
|
T60 |
45 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174451 |
1 |
|
|
T7 |
103 |
|
T8 |
609 |
|
T16 |
21 |
auto[1] |
3392 |
1 |
|
|
T7 |
2 |
|
T8 |
18 |
|
T16 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177843 |
1 |
|
|
T7 |
105 |
|
T8 |
627 |
|
T16 |
23 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177828 |
1 |
|
|
T7 |
105 |
|
T8 |
627 |
|
T16 |
23 |
auto[1] |
15 |
1 |
|
|
T80 |
1 |
|
T188 |
1 |
|
T68 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1186 |
1 |
|
|
T7 |
1 |
|
T8 |
9 |
|
T16 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3392 |
1 |
|
|
T7 |
2 |
|
T8 |
18 |
|
T16 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
190841 |
1 |
|
|
T7 |
19 |
|
T8 |
710 |
|
T23 |
4 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
104914 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61117 |
1 |
|
|
T7 |
18 |
|
T8 |
700 |
|
T23 |
4 |
seven_bytes |
3500 |
1 |
|
|
T9 |
29 |
|
T58 |
9 |
|
T60 |
40 |
six_bytes |
3520 |
1 |
|
|
T9 |
35 |
|
T58 |
3 |
|
T60 |
57 |
five_bytes |
3547 |
1 |
|
|
T9 |
35 |
|
T58 |
7 |
|
T60 |
37 |
four_bytes |
3670 |
1 |
|
|
T9 |
39 |
|
T58 |
8 |
|
T60 |
53 |
three_bytes |
3462 |
1 |
|
|
T9 |
27 |
|
T58 |
6 |
|
T60 |
30 |
two_bytes |
3520 |
1 |
|
|
T9 |
25 |
|
T58 |
4 |
|
T60 |
44 |
one_byte |
3591 |
1 |
|
|
T9 |
30 |
|
T58 |
8 |
|
T60 |
54 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
187283 |
1 |
|
|
T7 |
17 |
|
T8 |
690 |
|
T23 |
4 |
auto[1] |
3558 |
1 |
|
|
T7 |
2 |
|
T8 |
20 |
|
T9 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
190841 |
1 |
|
|
T7 |
19 |
|
T8 |
710 |
|
T23 |
4 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
190822 |
1 |
|
|
T7 |
19 |
|
T8 |
710 |
|
T23 |
4 |
auto[1] |
19 |
1 |
|
|
T10 |
1 |
|
T97 |
1 |
|
T189 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1162 |
1 |
|
|
T7 |
1 |
|
T8 |
10 |
|
T9 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3558 |
1 |
|
|
T7 |
2 |
|
T8 |
20 |
|
T9 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
369416 |
1 |
|
|
T8 |
902 |
|
T16 |
100 |
|
T9 |
1789 |
auto[1] |
523 |
1 |
|
|
T64 |
58 |
|
T67 |
5 |
|
T68 |
53 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
198624 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
124224 |
1 |
|
|
T8 |
887 |
|
T16 |
99 |
|
T9 |
39 |
seven_bytes |
6808 |
1 |
|
|
T9 |
55 |
|
T58 |
55 |
|
T60 |
91 |
six_bytes |
6730 |
1 |
|
|
T9 |
49 |
|
T58 |
61 |
|
T60 |
78 |
five_bytes |
6755 |
1 |
|
|
T9 |
54 |
|
T58 |
41 |
|
T60 |
95 |
four_bytes |
6774 |
1 |
|
|
T9 |
46 |
|
T58 |
37 |
|
T60 |
89 |
three_bytes |
6586 |
1 |
|
|
T9 |
34 |
|
T58 |
32 |
|
T60 |
83 |
two_bytes |
6761 |
1 |
|
|
T9 |
41 |
|
T58 |
56 |
|
T60 |
87 |
one_byte |
6677 |
1 |
|
|
T9 |
54 |
|
T58 |
48 |
|
T60 |
100 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
363006 |
1 |
|
|
T8 |
872 |
|
T16 |
98 |
|
T9 |
1769 |
auto[1] |
6933 |
1 |
|
|
T8 |
30 |
|
T16 |
2 |
|
T9 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
369939 |
1 |
|
|
T8 |
902 |
|
T16 |
100 |
|
T9 |
1789 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
369909 |
1 |
|
|
T8 |
902 |
|
T16 |
100 |
|
T9 |
1789 |
auto[1] |
30 |
1 |
|
|
T64 |
2 |
|
T10 |
1 |
|
T51 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2338 |
1 |
|
|
T8 |
15 |
|
T16 |
1 |
|
T9 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6933 |
1 |
|
|
T8 |
30 |
|
T16 |
2 |
|
T9 |
20 |