Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	264481502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

191036655

1

T1

177256

T2

342274

T3

177169

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	235339012	1			T1	229861		T2	451831		T3	226899
values[0x0]	105792244	1			T1	107826		T2	215020		T3	107146
values[0x1]	114386901	1			T1	117760		T2	234719		T3	115486

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	205414970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

250103187

1

T1

238810

T2

465213

T3

236611

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1316544	1			T1	1795		T2	3506		T3	1698
valid_sources[0x01]	1310842	1			T1	1742		T2	3542		T3	1797
valid_sources[0x02]	1327713	1			T1	1745		T2	3565		T3	1756
valid_sources[0x03]	1317036	1			T1	1776		T2	3536		T3	1778
valid_sources[0x04]	1333281	1			T1	1824		T2	3547		T3	1783
valid_sources[0x05]	1326605	1			T1	1770		T2	3477		T3	1802
valid_sources[0x06]	1410495	1			T1	1713		T2	3571		T3	1758
valid_sources[0x07]	1318228	1			T1	1696		T2	3473		T3	1761
valid_sources[0x08]	1972883	1			T1	1706		T2	3562		T3	1793
valid_sources[0x09]	1308162	1			T1	1805		T2	3579		T3	1709
valid_sources[0x0a]	1306363	1			T1	1843		T2	3583		T3	1757
valid_sources[0x0b]	1305171	1			T1	1714		T2	3486		T3	1796
valid_sources[0x0c]	1956555	1			T1	1721		T2	3675		T3	1741
valid_sources[0x0d]	6540027	1			T1	1725		T2	3480		T3	1742
valid_sources[0x0e]	2392530	1			T1	1775		T2	3481		T3	1796
valid_sources[0x0f]	2659328	1			T1	1786		T2	3522		T3	1828
valid_sources[0x10]	1321768	1			T1	1859		T2	3419		T3	1784
valid_sources[0x11]	1377784	1			T1	1792		T2	3405		T3	1729
valid_sources[0x12]	1300067	1			T1	1736		T2	3411		T3	1713
valid_sources[0x13]	3283675	1			T1	1720		T2	3520		T3	1810
valid_sources[0x14]	1320510	1			T1	1791		T2	3620		T3	1681
valid_sources[0x15]	1321827	1			T1	1817		T2	3525		T3	1781
valid_sources[0x16]	3281640	1			T1	1784		T2	3650		T3	1805
valid_sources[0x17]	1311208	1			T1	1704		T2	3612		T3	1729
valid_sources[0x18]	1307891	1			T1	1780		T2	3504		T3	1744
valid_sources[0x19]	1304678	1			T1	1762		T2	3514		T3	1798
valid_sources[0x1a]	1308679	1			T1	1836		T2	3619		T3	1731
valid_sources[0x1b]	1982301	1			T1	1862		T2	3578		T3	1832
valid_sources[0x1c]	1322252	1			T1	1806		T2	3496		T3	1730
valid_sources[0x1d]	1310501	1			T1	1788		T2	3463		T3	1800
valid_sources[0x1e]	1309763	1			T1	1777		T2	3406		T3	1740
valid_sources[0x1f]	1299061	1			T1	1801		T2	3519		T3	1679
valid_sources[0x20]	2211591	1			T1	1715		T2	3545		T3	1746
valid_sources[0x21]	1307204	1			T1	1762		T2	3523		T3	1703
valid_sources[0x22]	1329177	1			T1	1792		T2	3609		T3	1775
valid_sources[0x23]	1961068	1			T1	1789		T2	3494		T3	1743
valid_sources[0x24]	1415739	1			T1	1816		T2	3521		T3	1778
valid_sources[0x25]	2277154	1			T1	1781		T2	3621		T3	1724
valid_sources[0x26]	1311803	1			T1	1785		T2	3576		T3	1775
valid_sources[0x27]	1293780	1			T1	1784		T2	3519		T3	1730
valid_sources[0x28]	1299320	1			T1	1787		T2	3419		T3	1834
valid_sources[0x29]	3615372	1			T1	1783		T2	3572		T3	1724
valid_sources[0x2a]	1309800	1			T1	1721		T2	3478		T3	1696
valid_sources[0x2b]	1310158	1			T1	1754		T2	3545		T3	1741
valid_sources[0x2c]	1308825	1			T1	1800		T2	3555		T3	1690
valid_sources[0x2d]	1313741	1			T1	1758		T2	3589		T3	1784
valid_sources[0x2e]	1316595	1			T1	1775		T2	3533		T3	1795
valid_sources[0x2f]	2263856	1			T1	1778		T2	3655		T3	1720
valid_sources[0x30]	1316218	1			T1	1843		T2	3617		T3	1760
valid_sources[0x31]	2216523	1			T1	1754		T2	3493		T3	1720
valid_sources[0x32]	1657464	1			T1	1850		T2	3578		T3	1802
valid_sources[0x33]	2209153	1			T1	1795		T2	3629		T3	1736
valid_sources[0x34]	1320402	1			T1	1752		T2	3502		T3	1749
valid_sources[0x35]	1361994	1			T1	1743		T2	3566		T3	1805
valid_sources[0x36]	1317481	1			T1	1766		T2	3491		T3	1717
valid_sources[0x37]	1314974	1			T1	1768		T2	3507		T3	1822
valid_sources[0x38]	1994555	1			T1	1809		T2	3417		T3	1778
valid_sources[0x39]	1544563	1			T1	1733		T2	3469		T3	1790
valid_sources[0x3a]	1302809	1			T1	1777		T2	3452		T3	1702
valid_sources[0x3b]	3642608	1			T1	1724		T2	3461		T3	1697
valid_sources[0x3c]	1316212	1			T1	1801		T2	3505		T3	1711
valid_sources[0x3d]	2245272	1			T1	1805		T2	3519		T3	1741
valid_sources[0x3e]	2193961	1			T1	1802		T2	3565		T3	1757
valid_sources[0x3f]	1304014	1			T1	1690		T2	3519		T3	1763
valid_sources[0x40]	1343502	1			T1	1789		T2	3478		T3	1724
valid_sources[0x41]	1776636	1			T1	1732		T2	3402		T3	1690
valid_sources[0x42]	1971883	1			T1	1811		T2	3541		T3	1836
valid_sources[0x43]	1305101	1			T1	1774		T2	3552		T3	1769
valid_sources[0x44]	3671057	1			T1	1799		T2	3571		T3	1737
valid_sources[0x45]	1322961	1			T1	1788		T2	3561		T3	1794
valid_sources[0x46]	3606317	1			T1	1829		T2	3456		T3	1710
valid_sources[0x47]	2334445	1			T1	1759		T2	3395		T3	1775
valid_sources[0x48]	1315080	1			T1	1695		T2	3563		T3	1732
valid_sources[0x49]	1307874	1			T1	1838		T2	3553		T3	1763
valid_sources[0x4a]	1316806	1			T1	1839		T2	3610		T3	1746
valid_sources[0x4b]	1307722	1			T1	1823		T2	3559		T3	1727
valid_sources[0x4c]	1311463	1			T1	1783		T2	3552		T3	1811
valid_sources[0x4d]	1313879	1			T1	1759		T2	3558		T3	1703
valid_sources[0x4e]	2134884	1			T1	1768		T2	3492		T3	1732
valid_sources[0x4f]	1487109	1			T1	1738		T2	3628		T3	1737
valid_sources[0x50]	1309232	1			T1	1766		T2	3417		T3	1876
valid_sources[0x51]	1303872	1			T1	1793		T2	3419		T3	1744
valid_sources[0x52]	1961266	1			T1	1772		T2	3345		T3	1784
valid_sources[0x53]	1395455	1			T1	1790		T2	3544		T3	1736
valid_sources[0x54]	1309282	1			T1	1694		T2	3522		T3	1666
valid_sources[0x55]	1537088	1			T1	1715		T2	3539		T3	1770
valid_sources[0x56]	2232281	1			T1	1800		T2	3511		T3	1732
valid_sources[0x57]	2222175	1			T1	1793		T2	3511		T3	1832
valid_sources[0x58]	1308510	1			T1	1894		T2	3462		T3	1721
valid_sources[0x59]	1310467	1			T1	1683		T2	3637		T3	1689
valid_sources[0x5a]	1309458	1			T1	1863		T2	3591		T3	1707
valid_sources[0x5b]	1960038	1			T1	1731		T2	3387		T3	1721
valid_sources[0x5c]	1399396	1			T1	1764		T2	3453		T3	1750
valid_sources[0x5d]	1779380	1			T1	1797		T2	3439		T3	1734
valid_sources[0x5e]	1312893	1			T1	1872		T2	3513		T3	1730
valid_sources[0x5f]	1314210	1			T1	1739		T2	3599		T3	1689
valid_sources[0x60]	1316435	1			T1	1758		T2	3367		T3	1733
valid_sources[0x61]	2153159	1			T1	1684		T2	3542		T3	1774
valid_sources[0x62]	2634823	1			T1	1772		T2	3515		T3	1784
valid_sources[0x63]	1313988	1			T1	1757		T2	3568		T3	1744
valid_sources[0x64]	1406330	1			T1	1799		T2	3610		T3	1771
valid_sources[0x65]	1401854	1			T1	1815		T2	3473		T3	1778
valid_sources[0x66]	1300788	1			T1	1776		T2	3478		T3	1774
valid_sources[0x67]	1298315	1			T1	1789		T2	3546		T3	1773
valid_sources[0x68]	1765182	1			T1	1773		T2	3581		T3	1844
valid_sources[0x69]	1461334	1			T1	1851		T2	3507		T3	1760
valid_sources[0x6a]	1956399	1			T1	1676		T2	3468		T3	1639
valid_sources[0x6b]	1332449	1			T1	1692		T2	3646		T3	1764
valid_sources[0x6c]	1392554	1			T1	1847		T2	3550		T3	1775
valid_sources[0x6d]	1342646	1			T1	1764		T2	3662		T3	1748
valid_sources[0x6e]	2703648	1			T1	1777		T2	3544		T3	1707
valid_sources[0x6f]	3269220	1			T1	1752		T2	3524		T3	1824
valid_sources[0x70]	1307785	1			T1	1808		T2	3537		T3	1781
valid_sources[0x71]	1464220	1			T1	1852		T2	3519		T3	1808
valid_sources[0x72]	1306703	1			T1	1842		T2	3603		T3	1769
valid_sources[0x73]	1307854	1			T1	1818		T2	3523		T3	1763
valid_sources[0x74]	3336450	1			T1	1818		T2	3526		T3	1742
valid_sources[0x75]	3360985	1			T1	1837		T2	3545		T3	1799
valid_sources[0x76]	3269129	1			T1	1761		T2	3548		T3	1826
valid_sources[0x77]	1306043	1			T1	1787		T2	3665		T3	1737
valid_sources[0x78]	1778264	1			T1	1816		T2	3438		T3	1703
valid_sources[0x79]	3145474	1			T1	1817		T2	3514		T3	1756
valid_sources[0x7a]	2160670	1			T1	1792		T2	3487		T3	1712
valid_sources[0x7b]	2208580	1			T1	1770		T2	3514		T3	1698
valid_sources[0x7c]	1310766	1			T1	1795		T2	3485		T3	1724
valid_sources[0x7d]	1311723	1			T1	1740		T2	3541		T3	1805
valid_sources[0x7e]	1384929	1			T1	1802		T2	3489		T3	1756
valid_sources[0x7f]	2159411	1			T1	1793		T2	3518		T3	1714
valid_sources[0x80]	3283855	1			T1	1771		T2	3496		T3	1750

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73305781

1

T1

63605

T2

117363

T3

62767

values[0x0]

all_enables

biggest_size

63142736

1

T1

61190

T2

121596

T3

61913

values[0x1]

all_enables

biggest_size

54588138

1

T1

52461

T2

103315

T3

52489