Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

268069013

1

T1

278191

T2

559296

T3

272362

full_word

191260170

1

T1

177256

T2

342274

T3

177169

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	459328903	1			T1	455447		T2	901570		T3	449531
auto[TlIntgErrCmd]	84	1			T132	5		T133	9		T134	3
auto[TlIntgErrData]	105	1			T132	3		T134	5		T192	7
auto[TlIntgErrBoth]	91	1			T132	2		T133	1		T134	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236030064

1

T1

229861

T2

451831

T3

226899

auto[1]

223299119

1

T1

225586

T2

449739

T3

222632

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	162668066	1			T1	166256		T2	334468		T3	164132
auto[TlIntgErrNone]	partial	auto[1]	105400689	1			T1	111935		T2	224828		T3	108230
auto[TlIntgErrNone]	full_word	auto[0]	73361866	1			T1	63605		T2	117363		T3	62767
auto[TlIntgErrNone]	full_word	auto[1]	117898282	1			T1	113651		T2	224911		T3	114402
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T132	3		T133	6		T134	1
auto[TlIntgErrCmd]	partial	auto[1]	37	1			T132	2		T133	3		T134	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T174	1		T193	1		T195	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T192	1		T194	1		T196	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T132	1		T134	3		T192	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T132	2		T134	2		T192	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T192	2		T197	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T192	1		T190	1		T196	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T134	1		T192	6		T190	4
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T132	2		T133	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T198	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T190	1		T194	1		T199	1