Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	94.30	98.68	92.86		100.00	91.07	88.89

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	98.68	92.86		100.00	91.07	88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.80	98.88	92.86	100.00	100.00	91.38	91.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	429	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
423	1	1
429	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T7,T14
1	1	Covered	T13,T7,T14

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T13,T7,T14
0	1	Not Covered
1	0	Covered	T13,T7,T14

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T7,T14
1	1	Covered	T13,T7,T14

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T13,T7,T14
StKmacFlush	206	Covered	T13,T7,T14
StKmacIdle	181	Covered	T1,T2,T3
StKmacMsg	192	Covered	T13,T7,T14
StTerminalError	239	Covered	T15,T23,T24

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	192	Covered	T13,T7,T14
StKey->StTerminalError	239	Covered	T25,T33,T72
StKmacFlush->StKmacIdle	216	Covered	T13,T7,T14
StKmacFlush->StTerminalError	239	Covered	T38,T92,T94
StKmacIdle->StKey	179	Covered	T13,T7,T14
StKmacIdle->StTerminalError	239	Covered	T23,T24,T4
StKmacMsg->StKmacFlush	206	Covered	T13,T7,T14
StKmacMsg->StTerminalError	239	Covered	T15,T34,T90

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	418	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T13,T7,T14
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T13,T7,T14
StKey	-	0	-	-	Covered	T13,T7,T14
StKmacMsg	-	-	1	-	Covered	T13,T7,T14
StKmacMsg	-	-	0	-	Covered	T13,T7,T14
StKmacFlush	-	-	-	1	Covered	T13,T7,T14
StKmacFlush	-	-	-	0	Covered	T13,T7,T14
StTerminalError	-	-	-	-	Covered	T15,T23,T24
default	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T15,T23,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T3
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T2,T3
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	418	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T2,T11,T13
L256	Covered	T1,T2,T3
L384	Covered	T13,T7,T8
L512	Covered	T1,T3,T12
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T3
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T2,T3
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T3
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T2,T3
Key512	Covered	T1,T2,T3
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	9156208	0	0
KeyDataStable_M	2147483647	1074422	0	0
KeyLengthStable_M	2147483647	283209	0	0
KmacEnStable_M	2147483647	24048	0	0
MaxKeyLenMatchToKey512_A	1028	1028	0	0
ModeStable_M	2147483647	36569	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	43871	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9156208	0	0
T7	270686	4618	0	0
T8	269422	2691	0	0
T13	159126	327	0	0
T14	26141	109	0	0
T15	3893	0	0	0
T16	0	5057	0	0
T21	630526	0	0	0
T22	260524	0	0	0
T35	736037	58369	0	0
T57	987147	71504	0	0
T62	974059	0	0	0
T63	0	12	0	0
T95	0	355	0	0
T96	0	301	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1074422	0	0
T7	270686	2160	0	0
T8	269422	976	0	0
T13	159126	3776	0	0
T14	26141	8	0	0
T15	3893	32	0	0
T21	630526	0	0	0
T22	260524	0	0	0
T35	736037	2752	0	0
T57	987147	3424	0	0
T62	974059	0	0	0
T63	0	128	0	0
T95	0	4224	0	0
T96	0	3616	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	283209	0	0
T1	107905	193	0	0
T2	653396	314	0	0
T3	104312	187	0	0
T7	270686	76	0	0
T8	269422	107	0	0
T11	657080	314	0	0
T12	335366	196	0	0
T13	159126	118	0	0
T14	26141	1	0	0
T15	3893	1	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24048	0	0
T7	270686	35	0	0
T8	269422	42	0	0
T13	159126	53	0	0
T14	26141	1	0	0
T15	3893	1	0	0
T21	630526	0	0	0
T22	260524	0	0	0
T35	736037	37	0	0
T57	987147	60	0	0
T62	974059	0	0	0
T63	0	3	0	0
T95	0	61	0	0
T96	0	64	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36569	0	0
T7	270686	38	0	0
T8	269422	108	0	0
T13	159126	59	0	0
T14	26141	1	0	0
T15	3893	1	0	0
T21	630526	0	0	0
T22	260524	1	0	0
T35	736037	38	0	0
T57	987147	60	0	0
T62	974059	0	0	0
T63	0	3	0	0
T75	0	1	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43871	0	0
T1	107905	2	0	0
T2	653396	2	0	0
T3	104312	2	0	0
T7	270686	60	0	0
T8	269422	100	0	0
T11	657080	2	0	0
T12	335366	2	0	0
T13	159126	79	0	0
T14	26141	2	0	0
T15	3893	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107905	107899	0	0
T2	653396	653388	0	0
T3	104312	104306	0	0
T7	270686	270594	0	0
T8	269422	269347	0	0
T11	657080	657074	0	0
T12	335366	335357	0	0
T13	159126	159068	0	0
T14	26141	26058	0	0
T15	3893	3715	0	0

Line Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	75	98.68
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	3	3	100.00
ALWAYS	164	30	30	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
ALWAYS	266	6	5	83.33
CONT_ASSIGN	285	1	1	100.00
ALWAYS	305	6	6	100.00
ALWAYS	336	6	6	100.00
ALWAYS	336	6	6	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	429	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
159	3	3
164	1	1
166	1	1
167	1	1
169	1	1
171	1	1
172	1	1
174	1	1
176	1	1
178	1	1
179	1	1
181	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
197	1	1
199	1	1
205	1	1
206	1	1
208	1	1
210	1	1
215	1	1
216	1	1
218	1	1
224	1	1
225	1	1
238	1	1
239	1	1
			MISSING_ELSE
249	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
263	1	1
266	1	1
267	1	1
268	1	1
269	0	1
270	1	1
272	1	1
			MISSING_ELSE
285	1	1
305	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
336	1	1
339	1	1
343	1	1
347	1	1
351	1	1
356	1	1
370	1	1
373	1	1
392	1	1
418	1	1
419	1	1
420	1	1
421	1	1
422	1	1
423	1	1
429	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_core

	Total	Covered	Percent
Conditions	28	26	92.86
Logical	28	26	92.86
Non-Logical	0	0
Event	0	0

 LINE       178
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T7,T14
1	1	Covered	T13,T7,T14

 LINE       205
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T13,T7,T14
0	1	Not Covered
1	0	Covered	T13,T7,T14

 LINE       249
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       250
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       252
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       256
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       258
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       263
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

 LINE       268
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       392
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T7,T14
1	1	Covered	T13,T7,T14

 LINE       429
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T7,T14

---

FSM Coverage for Instance : tb.dut.u_kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	179	Covered	T13,T7,T14
StKmacFlush	206	Covered	T13,T7,T14
StKmacIdle	181	Covered	T1,T2,T3
StKmacMsg	192	Covered	T13,T7,T14
StTerminalError	239	Covered	T15,T23,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
StKey->StKmacMsg	192	Covered	T13,T7,T14
StKey->StTerminalError	239	Covered	T25,T33,T72
StKmacFlush->StKmacIdle	216	Covered	T13,T7,T14
StKmacFlush->StTerminalError	239	Excluded	T38,T92,T94	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StKmacIdle->StKey	179	Covered	T13,T7,T14
StKmacIdle->StTerminalError	239	Covered	T23,T24,T4
StKmacMsg->StKmacFlush	206	Covered	T13,T7,T14
StKmacMsg->StTerminalError	239	Covered	T15,T34,T90

---

Branch Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
Branches		56	51	91.07
TERNARY	249	2	2	100.00
TERNARY	250	2	2	100.00
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	256	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	263	2	2	100.00
IF	159	2	2	100.00
CASE	176	10	10	100.00
IF	238	2	2	100.00
IF	266	4	3	75.00
CASE	305	6	5	83.33
CASE	418	6	5	83.33
CASE	336	6	5	83.33
CASE	336	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	249	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	case (st)
-2-:	178	if ((kmac_en_i && start_i))
-3-:	191	if (sent_blocksize)
-4-:	205	if ((process_i || process_latched))
-5-:	215	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T13,T7,T14
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T13,T7,T14
StKey	-	0	-	-	Covered	T13,T7,T14
StKmacMsg	-	-	1	-	Covered	T13,T7,T14
StKmacMsg	-	-	0	-	Covered	T13,T7,T14
StKmacFlush	-	-	-	1	Covered	T13,T7,T14
StKmacFlush	-	-	-	0	Covered	T13,T7,T14
StTerminalError	-	-	-	-	Covered	T15,T23,T24
default	-	-	-	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	238	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T15,T23,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if ((process_i && (!process_o)))
-3-:	270	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T3
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T2,T3
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	418	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T2,T11,T13
L256	Covered	T1,T2,T3
L384	Covered	T13,T7,T8
L512	Covered	T1,T3,T12
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T3
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T2,T3
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	336	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T3
Key256	Covered	T1,T2,T3
Key384	Covered	T1,T2,T3
Key512	Covered	T1,T2,T3
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	8	88.89
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	8	88.89

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	2147483647	9156208	0	0
KeyDataStable_M	2147483647	1074422	0	0
KeyLengthStable_M	2147483647	283209	0	0
KmacEnStable_M	2147483647	24048	0	0
MaxKeyLenMatchToKey512_A	1028	1028	0	0
ModeStable_M	2147483647	36569	0	0
ProcessLatchedCleared_A	2147483647	0	0	0
StrengthStable_M	2147483647	43871	0	0
u_state_regs_A	2147483647	2147483647	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9156208	0	0
T7	270686	4618	0	0
T8	269422	2691	0	0
T13	159126	327	0	0
T14	26141	109	0	0
T15	3893	0	0	0
T16	0	5057	0	0
T21	630526	0	0	0
T22	260524	0	0	0
T35	736037	58369	0	0
T57	987147	71504	0	0
T62	974059	0	0	0
T63	0	12	0	0
T95	0	355	0	0
T96	0	301	0	0

KeyDataStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1074422	0	0
T7	270686	2160	0	0
T8	269422	976	0	0
T13	159126	3776	0	0
T14	26141	8	0	0
T15	3893	32	0	0
T21	630526	0	0	0
T22	260524	0	0	0
T35	736037	2752	0	0
T57	987147	3424	0	0
T62	974059	0	0	0
T63	0	128	0	0
T95	0	4224	0	0
T96	0	3616	0	0

KeyLengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	283209	0	0
T1	107905	193	0	0
T2	653396	314	0	0
T3	104312	187	0	0
T7	270686	76	0	0
T8	269422	107	0	0
T11	657080	314	0	0
T12	335366	196	0	0
T13	159126	118	0	0
T14	26141	1	0	0
T15	3893	1	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24048	0	0
T7	270686	35	0	0
T8	269422	42	0	0
T13	159126	53	0	0
T14	26141	1	0	0
T15	3893	1	0	0
T21	630526	0	0	0
T22	260524	0	0	0
T35	736037	37	0	0
T57	987147	60	0	0
T62	974059	0	0	0
T63	0	3	0	0
T95	0	61	0	0
T96	0	64	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36569	0	0
T7	270686	38	0	0
T8	269422	108	0	0
T13	159126	59	0	0
T14	26141	1	0	0
T15	3893	1	0	0
T21	630526	0	0	0
T22	260524	1	0	0
T35	736037	38	0	0
T57	987147	60	0	0
T62	974059	0	0	0
T63	0	3	0	0
T75	0	1	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43871	0	0
T1	107905	2	0	0
T2	653396	2	0	0
T3	104312	2	0	0
T7	270686	60	0	0
T8	269422	100	0	0
T11	657080	2	0	0
T12	335366	2	0	0
T13	159126	79	0	0
T14	26141	2	0	0
T15	3893	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107905	107899	0	0
T2	653396	653388	0	0
T3	104312	104306	0	0
T7	270686	270594	0	0
T8	269422	269347	0	0
T11	657080	657074	0	0
T12	335366	335357	0	0
T13	159126	159068	0	0
T14	26141	26058	0	0
T15	3893	3715	0	0