Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	823728	0	0
entropy_period_rd_A	2147483647	2637	0	0
intr_enable_rd_A	2147483647	3095	0	0
prefix_0_rd_A	2147483647	2012	0	0
prefix_10_rd_A	2147483647	2170	0	0
prefix_1_rd_A	2147483647	2067	0	0
prefix_2_rd_A	2147483647	2046	0	0
prefix_3_rd_A	2147483647	2164	0	0
prefix_4_rd_A	2147483647	2149	0	0
prefix_5_rd_A	2147483647	2127	0	0
prefix_6_rd_A	2147483647	2181	0	0
prefix_7_rd_A	2147483647	2201	0	0
prefix_8_rd_A	2147483647	2146	0	0
prefix_9_rd_A	2147483647	2104	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	823728	0	0
T48	204623	24900	0	0
T77	0	79873	0	0
T78	0	8675	0	0
T138	0	86595	0	0
T139	0	29896	0	0
T140	0	53687	0	0
T141	0	61913	0	0
T142	0	19233	0	0
T143	0	123507	0	0
T144	0	107524	0	0
T145	16343	0	0	0
T146	621603	0	0	0
T147	245620	0	0	0
T148	956035	0	0	0
T149	199174	0	0	0
T150	26165	0	0	0
T151	197205	0	0	0
T152	274507	0	0	0
T153	985821	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2637	0	0
T100	3974	23	0	0
T101	12285	67	0	0
T103	2779	16	0	0
T132	11727	59	0	0
T170	1784	1	0	0
T171	1773	12	0	0
T172	11427	34	0	0
T173	7938	18	0	0
T174	12335	76	0	0
T175	26305	181	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3095	0	0
T100	3974	24	0	0
T101	12285	91	0	0
T103	2779	4	0	0
T132	11727	98	0	0
T135	1341	6	0	0
T137	1488	15	0	0
T170	1784	18	0	0
T176	1099	12	0	0
T177	1143	23	0	0
T178	1660	28	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2012	0	0
T100	3974	14	0	0
T101	12285	61	0	0
T103	2779	10	0	0
T132	11727	43	0	0
T170	1784	8	0	0
T171	1773	4	0	0
T172	11427	31	0	0
T173	7938	13	0	0
T174	12335	56	0	0
T175	26305	215	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2170	0	0
T100	3974	17	0	0
T101	12285	49	0	0
T103	2779	3	0	0
T132	11727	50	0	0
T170	1784	5	0	0
T172	11427	87	0	0
T173	7938	7	0	0
T174	12335	37	0	0
T175	26305	183	0	0
T179	4877	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2067	0	0
T100	3974	13	0	0
T101	12285	46	0	0
T103	2779	8	0	0
T132	11727	46	0	0
T170	1784	5	0	0
T171	1773	5	0	0
T172	11427	49	0	0
T173	7938	16	0	0
T174	12335	48	0	0
T175	26305	199	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2046	0	0
T100	3974	10	0	0
T101	12285	69	0	0
T103	2779	14	0	0
T132	11727	29	0	0
T171	1773	1	0	0
T172	11427	32	0	0
T173	7938	19	0	0
T174	12335	29	0	0
T175	26305	191	0	0
T179	4877	4	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2164	0	0
T100	3974	19	0	0
T101	12285	56	0	0
T103	2779	6	0	0
T132	11727	42	0	0
T170	1784	7	0	0
T171	1773	8	0	0
T172	11427	57	0	0
T173	7938	22	0	0
T174	12335	32	0	0
T175	26305	247	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2149	0	0
T100	3974	17	0	0
T101	12285	56	0	0
T103	2779	6	0	0
T132	11727	20	0	0
T170	1784	2	0	0
T171	1773	7	0	0
T172	11427	98	0	0
T173	7938	26	0	0
T174	12335	35	0	0
T175	26305	224	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2127	0	0
T100	3974	15	0	0
T101	12285	45	0	0
T103	2779	8	0	0
T132	11727	31	0	0
T170	1784	2	0	0
T171	1773	4	0	0
T172	11427	48	0	0
T173	7938	19	0	0
T174	12335	51	0	0
T175	26305	186	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2181	0	0
T100	3974	16	0	0
T101	12285	68	0	0
T103	2779	7	0	0
T132	11727	40	0	0
T171	1773	6	0	0
T172	11427	68	0	0
T173	7938	24	0	0
T174	12335	44	0	0
T175	26305	216	0	0
T179	4877	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2201	0	0
T100	3974	17	0	0
T101	12285	57	0	0
T103	2779	5	0	0
T132	11727	50	0	0
T170	1784	7	0	0
T171	1773	7	0	0
T172	11427	45	0	0
T173	7938	6	0	0
T174	12335	34	0	0
T175	26305	230	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2146	0	0
T100	3974	23	0	0
T101	12285	48	0	0
T103	2779	4	0	0
T132	11727	45	0	0
T170	1784	4	0	0
T171	1773	1	0	0
T172	11427	70	0	0
T173	7938	24	0	0
T174	12335	41	0	0
T175	26305	191	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2104	0	0
T100	3974	24	0	0
T101	12285	48	0	0
T132	11727	55	0	0
T171	1773	3	0	0
T172	11427	64	0	0
T173	7938	12	0	0
T174	12335	27	0	0
T175	26305	238	0	0
T179	4877	6	0	0
T180	8209	28	0	0