Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166006 |
1 |
|
|
T1 |
323 |
|
T2 |
234 |
|
T8 |
489 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
84462 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61531 |
1 |
|
|
T1 |
318 |
|
T2 |
231 |
|
T8 |
481 |
seven_bytes |
2848 |
1 |
|
|
T10 |
12 |
|
T28 |
23 |
|
T29 |
12 |
six_bytes |
2904 |
1 |
|
|
T10 |
5 |
|
T28 |
36 |
|
T29 |
7 |
five_bytes |
2851 |
1 |
|
|
T10 |
10 |
|
T28 |
38 |
|
T29 |
14 |
four_bytes |
2890 |
1 |
|
|
T10 |
9 |
|
T28 |
43 |
|
T29 |
6 |
three_bytes |
2873 |
1 |
|
|
T10 |
14 |
|
T28 |
50 |
|
T29 |
12 |
two_bytes |
2793 |
1 |
|
|
T10 |
6 |
|
T28 |
28 |
|
T29 |
7 |
one_byte |
2854 |
1 |
|
|
T10 |
8 |
|
T28 |
38 |
|
T29 |
15 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162764 |
1 |
|
|
T1 |
313 |
|
T2 |
228 |
|
T8 |
473 |
auto[1] |
3242 |
1 |
|
|
T1 |
10 |
|
T2 |
6 |
|
T8 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166006 |
1 |
|
|
T1 |
323 |
|
T2 |
234 |
|
T8 |
489 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165997 |
1 |
|
|
T1 |
323 |
|
T2 |
234 |
|
T8 |
489 |
auto[1] |
9 |
1 |
|
|
T67 |
1 |
|
T20 |
1 |
|
T78 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1170 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T8 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3242 |
1 |
|
|
T1 |
10 |
|
T2 |
6 |
|
T8 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162232 |
1 |
|
|
T2 |
184 |
|
T8 |
730 |
|
T30 |
32 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
80403 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62921 |
1 |
|
|
T2 |
182 |
|
T8 |
204 |
|
T30 |
30 |
seven_bytes |
2731 |
1 |
|
|
T8 |
11 |
|
T10 |
15 |
|
T27 |
9 |
six_bytes |
2731 |
1 |
|
|
T8 |
16 |
|
T10 |
24 |
|
T27 |
9 |
five_bytes |
2700 |
1 |
|
|
T8 |
18 |
|
T10 |
20 |
|
T27 |
9 |
four_bytes |
2689 |
1 |
|
|
T8 |
25 |
|
T10 |
10 |
|
T27 |
7 |
three_bytes |
2765 |
1 |
|
|
T8 |
13 |
|
T10 |
27 |
|
T27 |
10 |
two_bytes |
2627 |
1 |
|
|
T8 |
11 |
|
T10 |
15 |
|
T27 |
6 |
one_byte |
2665 |
1 |
|
|
T8 |
9 |
|
T10 |
20 |
|
T27 |
8 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
159016 |
1 |
|
|
T2 |
180 |
|
T8 |
720 |
|
T30 |
28 |
auto[1] |
3216 |
1 |
|
|
T2 |
4 |
|
T8 |
10 |
|
T30 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162232 |
1 |
|
|
T2 |
184 |
|
T8 |
730 |
|
T30 |
32 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162219 |
1 |
|
|
T2 |
184 |
|
T8 |
730 |
|
T30 |
32 |
auto[1] |
13 |
1 |
|
|
T25 |
1 |
|
T174 |
1 |
|
T20 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1114 |
1 |
|
|
T2 |
2 |
|
T8 |
3 |
|
T30 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3216 |
1 |
|
|
T2 |
4 |
|
T8 |
10 |
|
T30 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332003 |
1 |
|
|
T1 |
159 |
|
T2 |
185 |
|
T8 |
959 |
auto[1] |
494 |
1 |
|
|
T19 |
43 |
|
T20 |
46 |
|
T21 |
84 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
169494 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
122647 |
1 |
|
|
T1 |
157 |
|
T2 |
182 |
|
T8 |
444 |
seven_bytes |
5716 |
1 |
|
|
T8 |
14 |
|
T10 |
20 |
|
T27 |
17 |
six_bytes |
5714 |
1 |
|
|
T8 |
12 |
|
T10 |
10 |
|
T27 |
14 |
five_bytes |
5802 |
1 |
|
|
T8 |
16 |
|
T10 |
13 |
|
T27 |
16 |
four_bytes |
5856 |
1 |
|
|
T8 |
13 |
|
T10 |
15 |
|
T27 |
16 |
three_bytes |
5796 |
1 |
|
|
T8 |
14 |
|
T10 |
18 |
|
T27 |
10 |
two_bytes |
5719 |
1 |
|
|
T8 |
11 |
|
T10 |
19 |
|
T27 |
20 |
one_byte |
5753 |
1 |
|
|
T8 |
21 |
|
T10 |
13 |
|
T27 |
11 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326089 |
1 |
|
|
T1 |
155 |
|
T2 |
179 |
|
T8 |
939 |
auto[1] |
6408 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T8 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332497 |
1 |
|
|
T1 |
159 |
|
T2 |
185 |
|
T8 |
959 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332481 |
1 |
|
|
T1 |
159 |
|
T2 |
185 |
|
T8 |
959 |
auto[1] |
16 |
1 |
|
|
T28 |
1 |
|
T58 |
1 |
|
T175 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2238 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T8 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6408 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T8 |
20 |