Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262226300

1

T1

78948

T2

42796

T3

5108

full_word

185864035

1

T1

109225

T2

63668

T3

23772

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448090035	1			T1	188173		T2	106464		T3	28880
auto[TlIntgErrCmd]	107	1			T124	4		T125	2		T126	5
auto[TlIntgErrData]	96	1			T124	2		T125	5		T126	3
auto[TlIntgErrBoth]	97	1			T124	4		T125	3		T126	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229863353

1

T1

124151

T2

70028

T3

16631

auto[1]

218226982

1

T1

64022

T2

36436

T3

12249

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158134205	1			T1	50883		T2	27052		T3	2860
auto[TlIntgErrNone]	partial	auto[1]	104091824	1			T1	28065		T2	15744		T3	2248
auto[TlIntgErrNone]	full_word	auto[0]	71729023	1			T1	73268		T2	42976		T3	13771
auto[TlIntgErrNone]	full_word	auto[1]	114134983	1			T1	35957		T2	20692		T3	10001
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T126	1		T176	1		T177	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T124	2		T125	2		T126	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T124	1		T126	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	13	1			T124	1		T177	1		T180	2
auto[TlIntgErrData]	partial	auto[0]	48	1			T124	1		T125	4		T176	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T124	1		T125	1		T126	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T180	2		T182	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T126	1		T181	1		T183	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T124	2		T176	3		T177	6
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T124	2		T125	2		T126	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T177	1		T180	1		T184	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T125	1		T177	1		T180	1