Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	881916	0	0
entropy_period_rd_A	2147483647	1329	0	0
intr_enable_rd_A	2147483647	2039	0	0
prefix_0_rd_A	2147483647	1269	0	0
prefix_10_rd_A	2147483647	1322	0	0
prefix_1_rd_A	2147483647	1318	0	0
prefix_2_rd_A	2147483647	1176	0	0
prefix_3_rd_A	2147483647	1293	0	0
prefix_4_rd_A	2147483647	1195	0	0
prefix_5_rd_A	2147483647	1318	0	0
prefix_6_rd_A	2147483647	1283	0	0
prefix_7_rd_A	2147483647	1273	0	0
prefix_8_rd_A	2147483647	1359	0	0
prefix_9_rd_A	2147483647	1186	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	881916	0	0
T8	712595	99949	0	0
T9	282900	0	0	0
T15	3874	0	0	0
T17	23376	0	0	0
T34	19436	0	0	0
T35	176671	0	0	0
T49	24635	0	0	0
T52	0	53487	0	0
T59	1081	0	0	0
T60	20237	0	0	0
T61	859327	0	0	0
T66	0	141527	0	0
T130	0	113615	0	0
T131	0	28160	0	0
T132	0	65056	0	0
T133	0	43042	0	0
T134	0	23432	0	0
T135	0	122848	0	0
T136	0	21153	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1329	0	0
T90	0	1	0	0
T91	0	73	0	0
T93	0	28	0	0
T124	0	18	0	0
T126	0	29	0	0
T133	450559	139	0	0
T154	0	81	0	0
T155	0	8	0	0
T156	0	9	0	0
T157	0	5	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2039	0	0
T90	0	11	0	0
T91	0	88	0	0
T93	0	43	0	0
T124	0	60	0	0
T126	0	66	0	0
T129	0	2	0	0
T133	450559	103	0	0
T154	0	43	0	0
T155	0	11	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0
T167	0	19	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1269	0	0
T90	0	4	0	0
T91	0	46	0	0
T93	0	32	0	0
T124	0	20	0	0
T126	0	11	0	0
T133	450559	140	0	0
T154	0	44	0	0
T155	0	8	0	0
T156	0	7	0	0
T157	0	11	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1322	0	0
T90	0	7	0	0
T91	0	56	0	0
T93	0	48	0	0
T124	0	23	0	0
T126	0	19	0	0
T133	450559	130	0	0
T154	0	65	0	0
T155	0	6	0	0
T156	0	13	0	0
T157	0	5	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1318	0	0
T90	0	9	0	0
T91	0	42	0	0
T93	0	25	0	0
T124	0	10	0	0
T126	0	16	0	0
T133	450559	138	0	0
T154	0	45	0	0
T155	0	14	0	0
T156	0	7	0	0
T157	0	11	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1176	0	0
T90	0	5	0	0
T91	0	62	0	0
T93	0	20	0	0
T124	0	7	0	0
T126	0	15	0	0
T133	450559	109	0	0
T154	0	35	0	0
T155	0	2	0	0
T156	0	8	0	0
T157	0	10	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1293	0	0
T90	0	8	0	0
T91	0	51	0	0
T93	0	29	0	0
T124	0	7	0	0
T126	0	26	0	0
T133	450559	154	0	0
T154	0	44	0	0
T155	0	5	0	0
T156	0	14	0	0
T157	0	15	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1195	0	0
T90	0	5	0	0
T91	0	41	0	0
T93	0	28	0	0
T124	0	31	0	0
T126	0	22	0	0
T133	450559	84	0	0
T154	0	55	0	0
T155	0	10	0	0
T156	0	1	0	0
T157	0	5	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1318	0	0
T90	0	8	0	0
T91	0	46	0	0
T93	0	19	0	0
T124	0	29	0	0
T126	0	13	0	0
T133	450559	108	0	0
T154	0	43	0	0
T155	0	9	0	0
T156	0	13	0	0
T157	0	6	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1283	0	0
T90	0	17	0	0
T91	0	40	0	0
T93	0	19	0	0
T124	0	18	0	0
T126	0	12	0	0
T133	450559	136	0	0
T154	0	60	0	0
T155	0	10	0	0
T156	0	7	0	0
T157	0	15	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1273	0	0
T90	0	11	0	0
T91	0	42	0	0
T93	0	18	0	0
T124	0	9	0	0
T126	0	19	0	0
T133	450559	112	0	0
T154	0	69	0	0
T156	0	11	0	0
T157	0	10	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0
T168	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1359	0	0
T90	0	4	0	0
T91	0	49	0	0
T93	0	35	0	0
T124	0	19	0	0
T126	0	11	0	0
T133	450559	148	0	0
T154	0	75	0	0
T155	0	7	0	0
T156	0	8	0	0
T157	0	16	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1186	0	0
T90	0	6	0	0
T91	0	57	0	0
T93	0	28	0	0
T124	0	15	0	0
T126	0	18	0	0
T133	450559	105	0	0
T154	0	58	0	0
T155	0	8	0	0
T156	0	3	0	0
T157	0	14	0	0
T158	27802	0	0	0
T159	43417	0	0	0
T160	526013	0	0	0
T161	14060	0	0	0
T162	362487	0	0	0
T163	106089	0	0	0
T164	701	0	0	0
T165	604683	0	0	0
T166	77705	0	0	0