Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260091309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185714539

1

T1

910955

T2

13

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	231337748	1			T1	119506		T2	1		T3	1
values[0x0]	103081602	1			T1	555617		T2	22		T3	11
values[0x1]	111386498	1			T1	605169		T2	18		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202075457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

243730391

1

T1

123014

T2

15

T3

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2233315	1			T1	9340		T4	312		T14	3658
valid_sources[0x01]	1415408	1			T1	9355		T4	331		T14	3532
valid_sources[0x02]	1308772	1			T1	8982		T4	310		T12	5
valid_sources[0x03]	1316757	1			T1	9085		T4	321		T14	3692
valid_sources[0x04]	1319788	1			T1	9173		T4	310		T12	2
valid_sources[0x05]	1313614	1			T1	9110		T4	309		T12	3
valid_sources[0x06]	1314297	1			T1	9295		T4	357		T12	1
valid_sources[0x07]	1402796	1			T1	9354		T4	306		T14	3669
valid_sources[0x08]	3256630	1			T1	9168		T4	295		T12	1
valid_sources[0x09]	2195956	1			T1	9068		T4	320		T14	3556
valid_sources[0x0a]	1310998	1			T1	9071		T4	329		T14	3562
valid_sources[0x0b]	2034222	1			T1	9216		T4	719121		T12	2
valid_sources[0x0c]	1974583	1			T1	9185		T3	30		T4	299
valid_sources[0x0d]	1312723	1			T1	9138		T4	305		T14	3575
valid_sources[0x0e]	1461899	1			T1	9402		T4	285		T14	3478
valid_sources[0x0f]	1312822	1			T1	9342		T4	304		T14	3462
valid_sources[0x10]	1313666	1			T1	9412		T4	324		T12	2
valid_sources[0x11]	1309727	1			T1	9278		T4	312		T14	3556
valid_sources[0x12]	1373149	1			T1	9184		T4	318		T12	1
valid_sources[0x13]	1756353	1			T1	9172		T4	295		T12	1
valid_sources[0x14]	1316160	1			T1	9030		T4	333		T12	3
valid_sources[0x15]	1779759	1			T1	9258		T4	299		T12	1
valid_sources[0x16]	1308165	1			T1	9352		T4	323		T14	3504
valid_sources[0x17]	1315834	1			T1	9315		T4	297		T14	3593
valid_sources[0x18]	3661648	1			T1	9169		T4	316		T12	1
valid_sources[0x19]	1315500	1			T1	9102		T4	334		T14	3634
valid_sources[0x1a]	1309146	1			T1	9122		T4	314		T14	3649
valid_sources[0x1b]	1956241	1			T1	9061		T4	346		T12	1
valid_sources[0x1c]	1312549	1			T1	9017		T4	314		T14	3744
valid_sources[0x1d]	1314473	1			T1	9353		T4	296		T14	3467
valid_sources[0x1e]	1368448	1			T1	9274		T4	320		T14	3737
valid_sources[0x1f]	2329818	1			T1	9214		T4	293		T14	3462
valid_sources[0x20]	1308659	1			T1	9228		T4	327		T14	3670
valid_sources[0x21]	1313299	1			T1	9073		T4	320		T14	3575
valid_sources[0x22]	1313495	1			T1	9210		T4	304		T12	1
valid_sources[0x23]	1312589	1			T1	9043		T4	307		T14	3550
valid_sources[0x24]	3295559	1			T1	9232		T4	281		T14	3512
valid_sources[0x25]	1311746	1			T1	9284		T4	325		T12	2
valid_sources[0x26]	2315143	1			T1	9177		T4	316		T14	3722
valid_sources[0x27]	1308642	1			T1	9264		T4	316		T14	3572
valid_sources[0x28]	1546705	1			T1	9094		T4	314		T14	3596
valid_sources[0x29]	1314360	1			T1	9399		T4	351		T12	1
valid_sources[0x2a]	1313314	1			T1	9218		T4	304		T12	4
valid_sources[0x2b]	1308679	1			T1	9201		T4	299		T12	2
valid_sources[0x2c]	1776163	1			T1	9389		T4	320		T14	3573
valid_sources[0x2d]	1308279	1			T1	9394		T4	334		T14	3549
valid_sources[0x2e]	2072531	1			T1	9289		T4	322		T12	1
valid_sources[0x2f]	1758484	1			T1	9255		T4	319		T12	2
valid_sources[0x30]	1312048	1			T1	8980		T4	322		T14	3477
valid_sources[0x31]	3416514	1			T1	9219		T4	308		T14	3602
valid_sources[0x32]	1975888	1			T1	9124		T4	312		T14	3458
valid_sources[0x33]	3477337	1			T1	9364		T4	340		T5	642040
valid_sources[0x34]	1312172	1			T1	9208		T4	320		T14	3544
valid_sources[0x35]	1785397	1			T1	9278		T4	284		T14	3564
valid_sources[0x36]	4604493	1			T1	9232		T4	350		T12	2
valid_sources[0x37]	1413443	1			T1	9306		T4	310		T14	3691
valid_sources[0x38]	1308770	1			T1	9094		T4	295		T14	3555
valid_sources[0x39]	1388708	1			T1	9140		T4	290		T12	2
valid_sources[0x3a]	1310422	1			T1	9271		T4	337		T14	3678
valid_sources[0x3b]	1312789	1			T1	9110		T4	290		T14	3540
valid_sources[0x3c]	1309451	1			T1	9152		T4	314		T14	3568
valid_sources[0x3d]	1316343	1			T1	9341		T4	338		T14	3560
valid_sources[0x3e]	1415549	1			T1	9113		T4	341		T12	2
valid_sources[0x3f]	1589177	1			T1	9049		T4	342		T12	1
valid_sources[0x40]	1311575	1			T1	9287		T4	310		T12	1
valid_sources[0x41]	2440390	1			T1	9371		T4	314		T14	3645
valid_sources[0x42]	1310142	1			T1	9254		T4	320		T14	3611
valid_sources[0x43]	2194352	1			T1	9227		T4	342		T12	1
valid_sources[0x44]	1770870	1			T1	9137		T4	318		T14	3523
valid_sources[0x45]	1319813	1			T1	9332		T4	324		T14	3702
valid_sources[0x46]	1972495	1			T1	9138		T4	324		T12	1
valid_sources[0x47]	1305950	1			T1	9150		T4	313		T14	3566
valid_sources[0x48]	1444489	1			T1	9382		T4	321		T12	2
valid_sources[0x49]	3280040	1			T1	9178		T4	294		T12	2
valid_sources[0x4a]	1313787	1			T1	8968		T4	298		T14	3717
valid_sources[0x4b]	1332588	1			T1	9476		T4	327		T14	3572
valid_sources[0x4c]	1310670	1			T1	9200		T4	296		T14	3608
valid_sources[0x4d]	1309514	1			T1	9216		T4	321		T14	3712
valid_sources[0x4e]	1311060	1			T1	9193		T4	328		T12	3
valid_sources[0x4f]	1309385	1			T1	9056		T4	314		T12	1
valid_sources[0x50]	1308704	1			T1	9293		T4	310		T14	3538
valid_sources[0x51]	2874921	1			T1	9113		T4	307		T14	3564
valid_sources[0x52]	3305216	1			T1	9197		T4	306		T12	1
valid_sources[0x53]	1483379	1			T1	9226		T4	334		T14	3524
valid_sources[0x54]	1309118	1			T1	9057		T4	320		T14	3576
valid_sources[0x55]	1312632	1			T1	9185		T4	293		T14	3571
valid_sources[0x56]	1408719	1			T1	9361		T4	298		T14	3562
valid_sources[0x57]	1313928	1			T1	9200		T4	307		T14	3628
valid_sources[0x58]	4153596	1			T1	9208		T4	322		T12	1
valid_sources[0x59]	1759309	1			T1	8985		T4	307		T12	4
valid_sources[0x5a]	1422745	1			T1	9183		T4	327		T14	3583
valid_sources[0x5b]	1313441	1			T1	9018		T4	342		T12	1
valid_sources[0x5c]	1310280	1			T1	9231		T4	299		T14	3528
valid_sources[0x5d]	1315778	1			T1	9227		T4	338		T12	1
valid_sources[0x5e]	1308890	1			T1	9522		T4	292		T12	2
valid_sources[0x5f]	1312719	1			T1	9170		T4	284		T14	3507
valid_sources[0x60]	1314182	1			T1	9402		T4	299		T12	2
valid_sources[0x61]	1436846	1			T1	9287		T4	314		T14	3791
valid_sources[0x62]	1494808	1			T1	9069		T4	309		T12	1
valid_sources[0x63]	2194415	1			T1	9216		T4	317		T12	1
valid_sources[0x64]	2065659	1			T1	9033		T4	324		T12	2
valid_sources[0x65]	1760797	1			T1	9296		T4	315		T14	3510
valid_sources[0x66]	1312161	1			T1	9026		T4	342		T12	2
valid_sources[0x67]	1437974	1			T1	9097		T4	301		T14	3511
valid_sources[0x68]	1306336	1			T1	9124		T4	326		T14	3567
valid_sources[0x69]	1310229	1			T1	9127		T4	304		T14	3588
valid_sources[0x6a]	1316579	1			T1	9190		T4	308		T12	1
valid_sources[0x6b]	1308985	1			T1	9135		T4	348		T14	3514
valid_sources[0x6c]	1317161	1			T1	9224		T4	336		T12	2
valid_sources[0x6d]	1311936	1			T1	9199		T4	313		T12	1
valid_sources[0x6e]	2170656	1			T1	9136		T4	315		T14	3685
valid_sources[0x6f]	1971542	1			T1	8995		T4	340		T14	3646
valid_sources[0x70]	3792713	1			T1	9255		T4	333		T14	3668
valid_sources[0x71]	3272800	1			T1	9268		T4	355		T14	3649
valid_sources[0x72]	1313954	1			T1	9076		T4	299		T14	3704
valid_sources[0x73]	1307725	1			T1	9350		T4	313		T12	1
valid_sources[0x74]	1316171	1			T1	9148		T4	303		T12	2
valid_sources[0x75]	1314936	1			T1	9167		T4	322		T14	3498
valid_sources[0x76]	2164603	1			T1	9353		T4	307		T14	3638
valid_sources[0x77]	1410196	1			T1	9077		T4	325		T12	1
valid_sources[0x78]	1928137	1			T1	9172		T4	319		T12	2
valid_sources[0x79]	1315491	1			T1	9272		T4	296		T14	3610
valid_sources[0x7a]	1320696	1			T1	9169		T4	332		T14	3737
valid_sources[0x7b]	1362673	1			T1	9212		T4	309		T14	3659
valid_sources[0x7c]	1310273	1			T1	9142		T4	302		T14	3592
valid_sources[0x7d]	1310529	1			T1	9223		T4	287		T14	3554
valid_sources[0x7e]	3656239	1			T1	8953		T4	327		T12	1
valid_sources[0x7f]	1309850	1			T1	9233		T4	299		T14	3556
valid_sources[0x80]	2205892	1			T1	9270		T4	311		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71695956

1

T1

339566

T2

1

T3

1

values[0x0]

all_enables

biggest_size

61219693

1

T1

310090

T2

9

T3

1

values[0x1]

all_enables

biggest_size

52798890

1

T1

261299

T2

3

T3

3