Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262237186

1

T1

144489

T2

28

T3

25

full_word

185849355

1

T1

910955

T2

13

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448086251	1			T1	235584		T2	41		T3	30
auto[TlIntgErrCmd]	108	1			T111	7		T112	6		T113	10
auto[TlIntgErrData]	90	1			T111	5		T112	9		T113	6
auto[TlIntgErrBoth]	92	1			T111	8		T112	5		T113	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231753872

1

T1

119506

T2

1

T3

1

auto[1]

216332669

1

T1

116078

T2

40

T3

29

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160023685	1			T1	855497		T4	296326		T5	235990
auto[TlIntgErrNone]	partial	auto[1]	102213229	1			T1	589397		T2	28		T3	25
auto[TlIntgErrNone]	full_word	auto[0]	71730065	1			T1	339566		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	114119272	1			T1	571389		T2	12		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T111	3		T112	6		T113	3
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T111	2		T113	6		T166	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T111	1		T113	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T111	1		T166	1		T167	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T111	1		T112	2		T113	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T111	4		T112	6		T113	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T112	1		T167	1		T168	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T167	1		T169	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T111	2		T112	1		T113	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T111	6		T112	4		T113	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T168	1		-	-		-	-