Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	491574	0	0
entropy_period_rd_A	2147483647	1873	0	0
intr_enable_rd_A	2147483647	2568	0	0
prefix_0_rd_A	2147483647	1945	0	0
prefix_10_rd_A	2147483647	1846	0	0
prefix_1_rd_A	2147483647	2013	0	0
prefix_2_rd_A	2147483647	1969	0	0
prefix_3_rd_A	2147483647	1787	0	0
prefix_4_rd_A	2147483647	1657	0	0
prefix_5_rd_A	2147483647	2060	0	0
prefix_6_rd_A	2147483647	1955	0	0
prefix_7_rd_A	2147483647	2006	0	0
prefix_8_rd_A	2147483647	1804	0	0
prefix_9_rd_A	2147483647	1795	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	491574	0	0
T9	108497	0	0	0
T10	158061	0	0	0
T11	0	31343	0	0
T18	104159	0	0	0
T19	431577	0	0	0
T36	252908	26528	0	0
T39	0	36522	0	0
T40	0	54526	0	0
T41	0	54994	0	0
T55	926034	0	0	0
T56	925823	0	0	0
T80	613246	0	0	0
T97	228990	0	0	0
T100	340714	0	0	0
T117	0	7415	0	0
T118	0	25288	0	0
T119	0	12102	0	0
T120	0	56744	0	0
T121	0	50605	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1873	0	0
T86	0	13	0	0
T112	0	122	0	0
T120	579066	50	0	0
T134	0	12	0	0
T135	0	64	0	0
T136	0	177	0	0
T137	0	28	0	0
T138	0	15	0	0
T139	0	17	0	0
T140	0	6	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2568	0	0
T86	0	7	0	0
T112	0	139	0	0
T120	579066	88	0	0
T134	0	12	0	0
T135	0	36	0	0
T136	0	474	0	0
T137	0	2	0	0
T138	0	1	0	0
T139	0	15	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T150	0	19	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1945	0	0
T86	0	7	0	0
T112	0	72	0	0
T120	579066	85	0	0
T134	0	13	0	0
T135	0	40	0	0
T136	0	491	0	0
T137	0	12	0	0
T138	0	4	0	0
T140	0	8	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T151	0	1	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1846	0	0
T86	0	24	0	0
T112	0	76	0	0
T120	579066	71	0	0
T134	0	9	0	0
T135	0	4	0	0
T136	0	410	0	0
T137	0	32	0	0
T138	0	1	0	0
T139	0	2	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T151	0	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2013	0	0
T86	0	10	0	0
T112	0	81	0	0
T120	579066	117	0	0
T134	0	12	0	0
T135	0	33	0	0
T136	0	375	0	0
T137	0	21	0	0
T139	0	3	0	0
T140	0	2	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T152	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1969	0	0
T86	0	3	0	0
T112	0	71	0	0
T120	579066	92	0	0
T134	0	11	0	0
T135	0	28	0	0
T136	0	458	0	0
T137	0	44	0	0
T138	0	9	0	0
T139	0	6	0	0
T140	0	5	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1787	0	0
T86	0	20	0	0
T112	0	72	0	0
T120	579066	105	0	0
T134	0	5	0	0
T135	0	29	0	0
T136	0	397	0	0
T137	0	1	0	0
T138	0	3	0	0
T140	0	12	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T151	0	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1657	0	0
T86	0	6	0	0
T112	0	66	0	0
T120	579066	64	0	0
T134	0	14	0	0
T135	0	7	0	0
T136	0	374	0	0
T137	0	15	0	0
T138	0	9	0	0
T140	0	6	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T153	0	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2060	0	0
T86	0	10	0	0
T112	0	77	0	0
T120	579066	136	0	0
T134	0	10	0	0
T135	0	56	0	0
T136	0	461	0	0
T138	0	7	0	0
T139	0	4	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T151	0	1	0	0
T154	0	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1955	0	0
T86	0	11	0	0
T112	0	60	0	0
T120	579066	71	0	0
T134	0	10	0	0
T135	0	72	0	0
T136	0	453	0	0
T137	0	26	0	0
T138	0	9	0	0
T139	0	4	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T151	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006	0	0
T86	0	20	0	0
T112	0	82	0	0
T120	579066	82	0	0
T134	0	2	0	0
T135	0	32	0	0
T136	0	429	0	0
T137	0	68	0	0
T138	0	7	0	0
T139	0	7	0	0
T140	0	14	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T86	0	12	0	0
T112	0	93	0	0
T120	579066	83	0	0
T134	0	3	0	0
T135	0	16	0	0
T136	0	427	0	0
T137	0	13	0	0
T138	0	1	0	0
T139	0	1	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0
T152	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1795	0	0
T86	0	23	0	0
T112	0	74	0	0
T120	579066	77	0	0
T134	0	9	0	0
T135	0	25	0	0
T136	0	398	0	0
T137	0	23	0	0
T138	0	2	0	0
T139	0	5	0	0
T140	0	13	0	0
T141	10000	0	0	0
T142	105240	0	0	0
T143	274924	0	0	0
T144	528989	0	0	0
T145	996	0	0	0
T146	14401	0	0	0
T147	3120	0	0	0
T148	179302	0	0	0
T149	192672	0	0	0