Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

270459939

1

T1

734

T2

6876

T3

40

full_word

191994294

1

T1

3384

T2

10572

T3

164

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	462453903	1			T1	4118		T2	17448		T3	204
auto[TlIntgErrCmd]	122	1			T124	3		T125	3		T126	3
auto[TlIntgErrData]	111	1			T124	2		T125	7		T126	8
auto[TlIntgErrBoth]	97	1			T124	5		T126	9		T166	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238041304

1

T1

2395

T2

11558

T3

87

auto[1]

224412929

1

T1

1723

T2

5890

T3

117

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	163654376	1			T1	398		T2	4314		T3	15
auto[TlIntgErrNone]	partial	auto[1]	106805260	1			T1	336		T2	2562		T3	25
auto[TlIntgErrNone]	full_word	auto[0]	74386787	1			T1	1997		T2	7244		T3	72
auto[TlIntgErrNone]	full_word	auto[1]	117607480	1			T1	1387		T2	3328		T3	92
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T124	1		T125	2		T166	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T124	2		T125	1		T126	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T169	1		T170	1		T171	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T126	1		T167	1		T172	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T124	1		T125	5		T126	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T124	1		T125	2		T126	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T169	1		T130	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T168	1		T169	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T124	1		T126	5		T167	5
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T124	3		T126	4		T166	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T124	1		T166	1		T167	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T131	1		T173	1		T174	1