Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	891154	0	0
entropy_period_rd_A	2147483647	2190	0	0
intr_enable_rd_A	2147483647	2890	0	0
prefix_0_rd_A	2147483647	2227	0	0
prefix_10_rd_A	2147483647	2058	0	0
prefix_1_rd_A	2147483647	2208	0	0
prefix_2_rd_A	2147483647	2064	0	0
prefix_3_rd_A	2147483647	2197	0	0
prefix_4_rd_A	2147483647	1935	0	0
prefix_5_rd_A	2147483647	2174	0	0
prefix_6_rd_A	2147483647	1986	0	0
prefix_7_rd_A	2147483647	2260	0	0
prefix_8_rd_A	2147483647	2213	0	0
prefix_9_rd_A	2147483647	2256	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	891154	0	0
T40	68885	0	0	0
T64	777268	69506	0	0
T65	479041	66932	0	0
T66	0	198720	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T132	0	23358	0	0
T133	0	39795	0	0
T134	0	23686	0	0
T135	0	66979	0	0
T136	0	68384	0	0
T137	0	18436	0	0
T138	0	58279	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2190	0	0
T40	68885	0	0	0
T64	777268	186	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	8	0	0
T96	0	53	0	0
T105	0	3	0	0
T134	0	90	0	0
T136	0	178	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	12	0	0
T152	0	138	0	0
T153	0	30	0	0
T154	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2890	0	0
T40	68885	0	0	0
T64	777268	128	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	10	0	0
T127	0	9	0	0
T128	0	4	0	0
T134	0	44	0	0
T136	0	162	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	20	0	0
T152	0	138	0	0
T153	0	24	0	0
T155	0	19	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T40	68885	0	0	0
T64	777268	158	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	8	0	0
T96	0	39	0	0
T105	0	2	0	0
T134	0	107	0	0
T136	0	147	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	10	0	0
T152	0	181	0	0
T153	0	59	0	0
T154	0	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2058	0	0
T40	68885	0	0	0
T64	777268	168	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	16	0	0
T96	0	37	0	0
T105	0	4	0	0
T134	0	51	0	0
T136	0	168	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	15	0	0
T152	0	98	0	0
T153	0	28	0	0
T154	0	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2208	0	0
T40	68885	0	0	0
T64	777268	197	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	8	0	0
T96	0	46	0	0
T105	0	7	0	0
T134	0	92	0	0
T136	0	108	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	17	0	0
T152	0	147	0	0
T153	0	33	0	0
T154	0	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2064	0	0
T40	68885	0	0	0
T64	777268	159	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	10	0	0
T96	0	45	0	0
T105	0	8	0	0
T134	0	51	0	0
T136	0	146	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	14	0	0
T152	0	173	0	0
T153	0	65	0	0
T154	0	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2197	0	0
T40	68885	0	0	0
T64	777268	196	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	8	0	0
T96	0	54	0	0
T105	0	4	0	0
T134	0	91	0	0
T136	0	156	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	22	0	0
T152	0	149	0	0
T153	0	36	0	0
T154	0	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1935	0	0
T40	68885	0	0	0
T64	777268	101	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	8	0	0
T96	0	37	0	0
T105	0	1	0	0
T134	0	68	0	0
T136	0	90	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	28	0	0
T152	0	141	0	0
T153	0	18	0	0
T154	0	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2174	0	0
T40	68885	0	0	0
T64	777268	157	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	8	0	0
T96	0	34	0	0
T105	0	4	0	0
T134	0	93	0	0
T136	0	135	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	35	0	0
T152	0	181	0	0
T153	0	66	0	0
T154	0	13	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1986	0	0
T40	68885	0	0	0
T64	777268	135	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	4	0	0
T96	0	26	0	0
T105	0	2	0	0
T134	0	59	0	0
T136	0	159	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	12	0	0
T152	0	130	0	0
T153	0	25	0	0
T154	0	1	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2260	0	0
T40	68885	0	0	0
T64	777268	171	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	10	0	0
T96	0	51	0	0
T105	0	10	0	0
T134	0	108	0	0
T136	0	140	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	34	0	0
T152	0	219	0	0
T153	0	34	0	0
T154	0	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2213	0	0
T40	68885	0	0	0
T64	777268	179	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	7	0	0
T96	0	53	0	0
T105	0	1	0	0
T134	0	52	0	0
T136	0	179	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	20	0	0
T152	0	154	0	0
T153	0	31	0	0
T154	0	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T40	68885	0	0	0
T64	777268	173	0	0
T65	479041	0	0	0
T75	2034	0	0	0
T92	12510	0	0	0
T95	0	2	0	0
T96	0	47	0	0
T134	0	89	0	0
T136	0	184	0	0
T139	442909	0	0	0
T140	26273	0	0	0
T141	155527	0	0	0
T142	492577	0	0	0
T143	580384	0	0	0
T151	0	19	0	0
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T153	0	31	0	0
T154	0	2	0	0
T156	0	246	0	0