Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265967368

1

T1

8657

T2

397015

T3

26384

full_word

188804226

1

T1

10655

T2

249984

T3

38152

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	454771264	1			T1	19312		T2	646999		T3	64536
auto[TlIntgErrCmd]	101	1			T114	4		T115	10		T116	3
auto[TlIntgErrData]	112	1			T114	3		T115	7		T116	5
auto[TlIntgErrBoth]	117	1			T114	3		T115	3		T116	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234314638

1

T1

12258

T2

325879

T3

42989

auto[1]

220456956

1

T1

7054

T2

321120

T3

21547

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161997511	1			T1	5384		T2	238527		T3	17071
auto[TlIntgErrNone]	partial	auto[1]	103969552	1			T1	3273		T2	158488		T3	9313
auto[TlIntgErrNone]	full_word	auto[0]	72316986	1			T1	6874		T2	87352		T3	25918
auto[TlIntgErrNone]	full_word	auto[1]	116487215	1			T1	3781		T2	162632		T3	12234
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T114	1		T115	4		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T114	3		T115	6		T116	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T169	1		T173	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T174	2		T173	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T114	2		T115	2		T116	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T115	5		T116	2		T165	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T165	1		T167	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T114	1		T175	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T114	1		T115	1		T116	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T114	2		T115	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T168	1		T172	2		T177	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T115	1		T166	1		T171	2