Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	695413	0	0
entropy_period_rd_A	2147483647	2581	0	0
intr_enable_rd_A	2147483647	3393	0	0
prefix_0_rd_A	2147483647	2395	0	0
prefix_10_rd_A	2147483647	2453	0	0
prefix_1_rd_A	2147483647	2515	0	0
prefix_2_rd_A	2147483647	2363	0	0
prefix_3_rd_A	2147483647	2385	0	0
prefix_4_rd_A	2147483647	2426	0	0
prefix_5_rd_A	2147483647	2389	0	0
prefix_6_rd_A	2147483647	2392	0	0
prefix_7_rd_A	2147483647	2552	0	0
prefix_8_rd_A	2147483647	2404	0	0
prefix_9_rd_A	2147483647	2486	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	695413	0	0
T13	2385	0	0	0
T19	129246	20445	0	0
T20	100596	0	0	0
T34	64540	0	0	0
T43	106403	91773	0	0
T44	662725	0	0	0
T53	0	28036	0	0
T62	0	80707	0	0
T76	193940	0	0	0
T80	483231	0	0	0
T101	10544	0	0	0
T102	12600	0	0	0
T110	0	56897	0	0
T120	0	13233	0	0
T121	0	15682	0	0
T122	0	57454	0	0
T123	0	14289	0	0
T124	0	39782	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2581	0	0
T82	0	40	0	0
T86	0	48	0	0
T95	0	19	0	0
T114	0	51	0	0
T136	760772	127	0	0
T137	0	89	0	0
T138	0	106	0	0
T139	0	15	0	0
T140	0	11	0	0
T141	0	4	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3393	0	0
T82	0	29	0	0
T114	0	75	0	0
T117	0	3	0	0
T136	760772	123	0	0
T137	0	66	0	0
T138	0	128	0	0
T139	0	14	0	0
T140	0	13	0	0
T141	0	15	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0
T151	0	2	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2395	0	0
T82	0	35	0	0
T86	0	34	0	0
T95	0	8	0	0
T114	0	34	0	0
T136	760772	141	0	0
T137	0	51	0	0
T138	0	130	0	0
T139	0	6	0	0
T140	0	11	0	0
T141	0	9	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2453	0	0
T82	0	21	0	0
T86	0	39	0	0
T95	0	12	0	0
T114	0	41	0	0
T136	760772	144	0	0
T137	0	62	0	0
T138	0	73	0	0
T139	0	28	0	0
T140	0	2	0	0
T141	0	3	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2515	0	0
T82	0	26	0	0
T86	0	27	0	0
T95	0	12	0	0
T114	0	24	0	0
T136	760772	126	0	0
T137	0	56	0	0
T138	0	119	0	0
T139	0	21	0	0
T140	0	4	0	0
T141	0	6	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2363	0	0
T82	0	27	0	0
T86	0	23	0	0
T95	0	15	0	0
T114	0	41	0	0
T136	760772	130	0	0
T137	0	37	0	0
T138	0	115	0	0
T139	0	59	0	0
T140	0	7	0	0
T141	0	2	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2385	0	0
T82	0	25	0	0
T86	0	32	0	0
T95	0	7	0	0
T114	0	38	0	0
T136	760772	161	0	0
T137	0	58	0	0
T138	0	66	0	0
T139	0	47	0	0
T140	0	13	0	0
T141	0	3	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2426	0	0
T82	0	24	0	0
T86	0	32	0	0
T95	0	8	0	0
T114	0	31	0	0
T136	760772	122	0	0
T137	0	35	0	0
T138	0	85	0	0
T139	0	23	0	0
T140	0	11	0	0
T141	0	5	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2389	0	0
T82	0	26	0	0
T86	0	42	0	0
T95	0	21	0	0
T114	0	46	0	0
T136	760772	80	0	0
T137	0	57	0	0
T138	0	129	0	0
T139	0	34	0	0
T140	0	9	0	0
T141	0	7	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2392	0	0
T82	0	40	0	0
T86	0	36	0	0
T95	0	24	0	0
T114	0	42	0	0
T136	760772	143	0	0
T137	0	44	0	0
T138	0	77	0	0
T139	0	2	0	0
T140	0	9	0	0
T141	0	9	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2552	0	0
T82	0	33	0	0
T86	0	21	0	0
T95	0	30	0	0
T114	0	30	0	0
T136	760772	171	0	0
T137	0	35	0	0
T138	0	85	0	0
T139	0	9	0	0
T140	0	7	0	0
T141	0	9	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T82	0	38	0	0
T86	0	46	0	0
T95	0	16	0	0
T114	0	28	0	0
T136	760772	118	0	0
T137	0	63	0	0
T138	0	116	0	0
T139	0	23	0	0
T140	0	5	0	0
T141	0	9	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2486	0	0
T82	0	27	0	0
T86	0	11	0	0
T95	0	5	0	0
T114	0	41	0	0
T136	760772	140	0	0
T137	0	92	0	0
T138	0	78	0	0
T139	0	38	0	0
T140	0	12	0	0
T141	0	7	0	0
T142	70364	0	0	0
T143	312781	0	0	0
T144	260020	0	0	0
T145	307252	0	0	0
T146	313669	0	0	0
T147	2608	0	0	0
T148	314125	0	0	0
T149	3730	0	0	0
T150	217721	0	0	0