Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259179086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185624749

1

T1

802

T2

5

T3

93300

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230299813	1			T1	61		T2	1		T3	105983
values[0x0]	103053441	1			T1	425		T2	7		T3	26335
values[0x1]	111450581	1			T1	384		T2	14		T3	28495

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201405512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

243398323

1

T1

816

T2

8

T3

109176

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3692452	1			T1	5		T3	627		T4	4
valid_sources[0x01]	4153135	1			T1	1		T3	630		T4	5
valid_sources[0x02]	1310545	1			T3	593		T4	6		T5	9
valid_sources[0x03]	1759447	1			T3	678		T4	8		T5	9
valid_sources[0x04]	1313316	1			T1	6		T3	610		T4	8
valid_sources[0x05]	2162809	1			T1	4		T3	605		T4	5
valid_sources[0x06]	1313895	1			T1	1		T3	696		T4	7
valid_sources[0x07]	3658006	1			T1	1		T2	1		T3	613
valid_sources[0x08]	1326926	1			T3	689		T4	4		T5	5
valid_sources[0x09]	1322400	1			T1	10		T3	629		T4	12
valid_sources[0x0a]	1767615	1			T1	1		T3	603		T4	7
valid_sources[0x0b]	2120791	1			T1	4		T3	641		T4	4
valid_sources[0x0c]	1420601	1			T1	2		T3	588		T4	9
valid_sources[0x0d]	2557184	1			T1	2		T3	603		T4	17
valid_sources[0x0e]	1315432	1			T1	3		T3	609		T4	14
valid_sources[0x0f]	1316013	1			T1	2		T3	622		T4	5
valid_sources[0x10]	1316581	1			T1	1		T3	611		T4	2
valid_sources[0x11]	2109744	1			T1	3		T3	644		T4	10
valid_sources[0x12]	1776398	1			T1	6		T3	613		T4	4
valid_sources[0x13]	1319296	1			T3	657		T4	2		T5	10
valid_sources[0x14]	1512514	1			T1	1		T3	619		T4	9
valid_sources[0x15]	1318111	1			T1	2		T3	622		T4	3
valid_sources[0x16]	1743690	1			T1	10		T3	675		T4	4
valid_sources[0x17]	1314082	1			T1	5		T3	623		T4	9
valid_sources[0x18]	1328002	1			T3	629		T4	14		T5	8
valid_sources[0x19]	2365391	1			T1	1		T3	623		T4	2
valid_sources[0x1a]	1316265	1			T1	1		T3	673		T4	2
valid_sources[0x1b]	1313131	1			T1	4		T2	1		T3	622
valid_sources[0x1c]	1310890	1			T3	598		T4	2		T5	3
valid_sources[0x1d]	1406451	1			T1	4		T3	610		T4	4
valid_sources[0x1e]	1313031	1			T1	3		T3	616		T4	24
valid_sources[0x1f]	1322194	1			T1	5		T3	662		T4	11
valid_sources[0x20]	1311519	1			T1	6		T3	608		T4	1
valid_sources[0x21]	1320211	1			T1	4		T2	2		T3	588
valid_sources[0x22]	1480604	1			T1	5		T2	2		T3	594
valid_sources[0x23]	1318456	1			T1	11		T3	615		T4	7
valid_sources[0x24]	1313758	1			T1	1		T3	637		T4	18
valid_sources[0x25]	1391045	1			T1	2		T3	635		T4	5
valid_sources[0x26]	1323686	1			T1	1		T2	1		T3	626
valid_sources[0x27]	1310982	1			T1	3		T3	654		T4	6
valid_sources[0x28]	1320782	1			T1	3		T3	664		T4	7
valid_sources[0x29]	1437089	1			T3	636		T4	2		T5	3
valid_sources[0x2a]	1314088	1			T3	638		T4	3		T5	6
valid_sources[0x2b]	1316780	1			T1	4		T3	624		T4	6
valid_sources[0x2c]	3644854	1			T3	597		T4	9		T5	5
valid_sources[0x2d]	1329297	1			T1	5		T3	660		T4	2
valid_sources[0x2e]	1316182	1			T1	2		T3	673		T4	24
valid_sources[0x2f]	1311651	1			T1	4		T3	628		T4	7
valid_sources[0x30]	1360373	1			T1	1		T3	601		T4	24
valid_sources[0x31]	1454787	1			T1	1		T3	625		T4	4
valid_sources[0x32]	1312497	1			T1	3		T3	606		T5	11
valid_sources[0x33]	1322013	1			T1	6		T3	609		T5	14
valid_sources[0x34]	1319807	1			T1	8		T3	646		T4	8
valid_sources[0x35]	1315195	1			T1	5		T3	673		T4	13
valid_sources[0x36]	1305476	1			T1	6		T3	640		T4	3
valid_sources[0x37]	1310885	1			T3	596		T4	6		T5	4
valid_sources[0x38]	1776136	1			T1	10		T3	623		T4	1
valid_sources[0x39]	1320601	1			T1	3		T3	649		T4	4
valid_sources[0x3a]	1322340	1			T3	592		T4	2		T5	3
valid_sources[0x3b]	1313254	1			T1	13		T3	655		T4	1
valid_sources[0x3c]	1309768	1			T1	2		T3	579		T4	14
valid_sources[0x3d]	1318628	1			T1	5		T3	687		T4	12
valid_sources[0x3e]	1312359	1			T1	8		T3	637		T4	26
valid_sources[0x3f]	1309240	1			T1	5		T3	644		T4	11
valid_sources[0x40]	1313393	1			T1	7		T3	657		T5	13
valid_sources[0x41]	1318364	1			T1	4		T3	682		T4	13
valid_sources[0x42]	3299499	1			T1	2		T3	613		T4	2
valid_sources[0x43]	2224811	1			T1	1		T3	678		T4	2
valid_sources[0x44]	1310373	1			T1	1		T3	624		T4	9
valid_sources[0x45]	1319833	1			T1	7		T3	647		T4	17
valid_sources[0x46]	1317931	1			T1	6		T3	629		T4	8
valid_sources[0x47]	4122308	1			T1	1		T3	600		T4	6
valid_sources[0x48]	1969448	1			T1	3		T3	646		T4	4
valid_sources[0x49]	1314725	1			T1	6		T3	609		T5	3
valid_sources[0x4a]	1307402	1			T3	589		T4	11		T5	3
valid_sources[0x4b]	2165603	1			T1	10		T3	597		T4	4
valid_sources[0x4c]	1316234	1			T3	676		T4	5		T5	6
valid_sources[0x4d]	1588560	1			T1	6		T2	1		T3	633
valid_sources[0x4e]	1311023	1			T1	10		T3	576		T4	3
valid_sources[0x4f]	1314537	1			T1	3		T3	627		T4	1
valid_sources[0x50]	1324357	1			T1	7		T3	630		T4	9
valid_sources[0x51]	1832150	1			T1	3		T3	655		T4	4
valid_sources[0x52]	3282594	1			T1	1		T2	1		T3	586
valid_sources[0x53]	1315738	1			T1	3		T3	632		T4	10
valid_sources[0x54]	1314578	1			T1	3		T3	627		T4	13
valid_sources[0x55]	1315930	1			T1	4		T3	627		T4	2
valid_sources[0x56]	1318398	1			T1	1		T3	615		T4	17
valid_sources[0x57]	1320976	1			T1	6		T3	602		T4	4
valid_sources[0x58]	1317318	1			T1	3		T2	1		T3	591
valid_sources[0x59]	1316375	1			T1	2		T3	549		T4	5
valid_sources[0x5a]	1313807	1			T1	2		T3	620		T4	15
valid_sources[0x5b]	1987054	1			T2	2		T3	657		T4	2
valid_sources[0x5c]	1317700	1			T1	2		T3	659		T5	7
valid_sources[0x5d]	2185492	1			T1	4		T3	648		T5	4
valid_sources[0x5e]	1315884	1			T1	1		T3	626		T4	10
valid_sources[0x5f]	1323612	1			T1	1		T3	564		T4	2
valid_sources[0x60]	1312725	1			T3	606		T4	6		T5	10
valid_sources[0x61]	1327957	1			T3	628		T5	11		T12	555
valid_sources[0x62]	1321649	1			T1	6		T3	611		T4	10
valid_sources[0x63]	1311880	1			T3	590		T4	11		T5	12
valid_sources[0x64]	1312397	1			T1	3		T3	559		T4	7
valid_sources[0x65]	1362130	1			T3	632		T4	22		T5	4
valid_sources[0x66]	3701604	1			T1	2		T3	642		T4	5
valid_sources[0x67]	1764289	1			T1	1		T3	667		T4	7
valid_sources[0x68]	1326212	1			T3	612		T4	14		T5	6
valid_sources[0x69]	1326313	1			T1	4		T3	637		T4	1
valid_sources[0x6a]	1308718	1			T1	3		T2	1		T3	650
valid_sources[0x6b]	1319109	1			T1	7		T3	644		T4	7
valid_sources[0x6c]	1306495	1			T1	5		T3	600		T4	1
valid_sources[0x6d]	1463051	1			T1	1		T3	628		T4	3
valid_sources[0x6e]	1490515	1			T1	1		T3	656		T4	17
valid_sources[0x6f]	1311913	1			T3	636		T4	8		T5	10
valid_sources[0x70]	1323460	1			T1	1		T3	649		T4	3
valid_sources[0x71]	1308228	1			T1	1		T3	624		T5	3
valid_sources[0x72]	2667584	1			T1	1		T3	594		T4	2
valid_sources[0x73]	1317376	1			T1	4		T3	612		T5	4
valid_sources[0x74]	1315493	1			T2	1		T3	643		T4	7
valid_sources[0x75]	1349432	1			T1	1		T3	642		T4	3
valid_sources[0x76]	1314216	1			T3	620		T4	8		T5	9
valid_sources[0x77]	1307808	1			T1	9		T3	664		T4	13
valid_sources[0x78]	1313019	1			T1	3		T3	623		T4	2
valid_sources[0x79]	1313807	1			T1	2		T3	643		T4	22
valid_sources[0x7a]	2168659	1			T1	2		T3	618		T4	4
valid_sources[0x7b]	1320917	1			T1	3		T3	609		T4	4
valid_sources[0x7c]	1313524	1			T1	9		T3	651		T4	8
valid_sources[0x7d]	1956301	1			T1	5		T3	632		T4	11
valid_sources[0x7e]	3600087	1			T1	4		T3	580		T4	13
valid_sources[0x7f]	1533572	1			T1	4		T3	651		T4	2
valid_sources[0x80]	1313719	1			T3	649		T4	1		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71713100

1

T1

26

T3

62632

T4

354

values[0x0]

all_enables

biggest_size

61161085

1

T1

407

T2

2

T3

16200

values[0x1]

all_enables

biggest_size

52750564

1

T1

369

T2

3

T3

14468