Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262524465

1

T1

68

T2

17

T3

67513

full_word

185835721

1

T1

802

T2

5

T3

93300

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448359876	1			T1	870		T2	22		T3	160813
auto[TlIntgErrCmd]	93	1			T125	5		T126	6		T127	3
auto[TlIntgErrData]	113	1			T125	4		T126	2		T127	4
auto[TlIntgErrBoth]	104	1			T125	1		T126	12		T127	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230946999

1

T1

61

T2

1

T3

105983

auto[1]

217413187

1

T1

809

T2

21

T3

54830

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159181050	1			T1	35		T2	1		T3	43351
auto[TlIntgErrNone]	partial	auto[1]	103343130	1			T1	33		T2	16		T3	24162
auto[TlIntgErrNone]	full_word	auto[0]	71765808	1			T1	26		T3	62632		T4	354
auto[TlIntgErrNone]	full_word	auto[1]	114069888	1			T1	776		T2	5		T3	30668
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T125	2		T126	2		T127	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T125	3		T126	4		T127	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T167	1		T170	1		T171	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T172	1		T167	2		T171	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T125	2		T126	1		T127	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T168	3		T172	5		T169	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T125	1		T126	1		T170	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T125	1		T167	1		T173	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T126	3		T127	3		T172	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T125	1		T126	9		T168	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T168	2		T172	1		T174	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T169	1		T175	1		T176	1