Unified Coverage Report :: Module :: kmac_reg_top

Module : kmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.46			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.87	100.00	99.46			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.88	99.27	96.48	100.00		98.63	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_cfg_regwen	100.00	100.00
u_cfg_shadowed0_qe	100.00	100.00				100.00
u_cfg_shadowed_en_unsupported_modestrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_fast_process	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_ready	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_err_processed	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kmac_en	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kstrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_endianness	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_mask	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_sideload	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_state_endianness	98.66	100.00	94.64			100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_cmd	100.00	100.00
u_cmd_entropy_req	100.00	100.00
u_cmd_hash_cnt_clr	100.00	100.00
u_entropy_period_prescaler	100.00	100.00	100.00			100.00
u_entropy_period_wait_timer	100.00	100.00	100.00			100.00
u_entropy_refresh_hash_cnt	62.59	77.78	50.00			60.00
u_entropy_refresh_threshold_shadowed	98.66	100.00	94.64			100.00	100.00
u_entropy_seed	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_kmac_done	100.00	100.00	100.00			100.00
u_intr_enable_kmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	62.59	77.78	50.00			60.00
u_intr_state_kmac_done	100.00	100.00	100.00			100.00
u_intr_state_kmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_kmac_done	100.00	100.00
u_intr_test_kmac_err	100.00	100.00
u_key_len	100.00	100.00	100.00			100.00
u_key_share0_0	100.00	100.00
u_key_share0_1	100.00	100.00
u_key_share0_10	100.00	100.00
u_key_share0_11	100.00	100.00
u_key_share0_12	100.00	100.00
u_key_share0_13	100.00	100.00
u_key_share0_14	100.00	100.00
u_key_share0_15	100.00	100.00
u_key_share0_2	100.00	100.00
u_key_share0_3	100.00	100.00
u_key_share0_4	100.00	100.00
u_key_share0_5	100.00	100.00
u_key_share0_6	100.00	100.00
u_key_share0_7	100.00	100.00
u_key_share0_8	100.00	100.00
u_key_share0_9	100.00	100.00
u_key_share1_0	100.00	100.00
u_key_share1_1	100.00	100.00
u_key_share1_10	100.00	100.00
u_key_share1_11	100.00	100.00
u_key_share1_12	100.00	100.00
u_key_share1_13	100.00	100.00
u_key_share1_14	100.00	100.00
u_key_share1_15	100.00	100.00
u_key_share1_2	100.00	100.00
u_key_share1_3	100.00	100.00
u_key_share1_4	100.00	100.00
u_key_share1_5	100.00	100.00
u_key_share1_6	100.00	100.00
u_key_share1_7	100.00	100.00
u_key_share1_8	100.00	100.00
u_key_share1_9	100.00	100.00
u_prefix_0	100.00	100.00	100.00			100.00
u_prefix_1	100.00	100.00	100.00			100.00
u_prefix_10	100.00	100.00	100.00			100.00
u_prefix_2	100.00	100.00	100.00			100.00
u_prefix_3	100.00	100.00	100.00			100.00
u_prefix_4	100.00	100.00	100.00			100.00
u_prefix_5	100.00	100.00	100.00			100.00
u_prefix_6	100.00	100.00	100.00			100.00
u_prefix_7	100.00	100.00	100.00			100.00
u_prefix_8	100.00	100.00	100.00			100.00
u_prefix_9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	91.58	96.18	82.65			87.50	100.00
u_status_alert_fatal_fault	100.00	100.00
u_status_alert_recov_ctrl_update_err	100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_status_sha3_absorb	100.00	100.00
u_status_sha3_idle	100.00	100.00
u_status_sha3_squeeze	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		499	499	100.00
ALWAYS	77	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
ALWAYS	136	3	3	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	618	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	740	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	814	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	888	1	1	100.00
CONT_ASSIGN	925	1	1	100.00
CONT_ASSIGN	962	1	1	100.00
CONT_ASSIGN	999	1	1	100.00
CONT_ASSIGN	1036	1	1	100.00
CONT_ASSIGN	1073	1	1	100.00
CONT_ASSIGN	1110	1	1	100.00
CONT_ASSIGN	1116	1	1	100.00
CONT_ASSIGN	1131	1	1	100.00
CONT_ASSIGN	1147	1	1	100.00
CONT_ASSIGN	1163	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1378	1	1	100.00
CONT_ASSIGN	1419	1	1	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1440	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1457	1	1	100.00
CONT_ASSIGN	1464	1	1	100.00
CONT_ASSIGN	1467	1	1	100.00
CONT_ASSIGN	1481	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1505	1	1	100.00
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1515	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1536	1	1	100.00
CONT_ASSIGN	1539	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1587	1	1	100.00
CONT_ASSIGN	1601	1	1	100.00
CONT_ASSIGN	1608	1	1	100.00
CONT_ASSIGN	1611	1	1	100.00
CONT_ASSIGN	1625	1	1	100.00
CONT_ASSIGN	1632	1	1	100.00
CONT_ASSIGN	1635	1	1	100.00
CONT_ASSIGN	1649	1	1	100.00
CONT_ASSIGN	1656	1	1	100.00
CONT_ASSIGN	1659	1	1	100.00
CONT_ASSIGN	1673	1	1	100.00
CONT_ASSIGN	1680	1	1	100.00
CONT_ASSIGN	1683	1	1	100.00
CONT_ASSIGN	1697	1	1	100.00
CONT_ASSIGN	1704	1	1	100.00
CONT_ASSIGN	1707	1	1	100.00
CONT_ASSIGN	1721	1	1	100.00
CONT_ASSIGN	1728	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1745	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1769	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1793	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1841	1	1	100.00
CONT_ASSIGN	1848	1	1	100.00
CONT_ASSIGN	1851	1	1	100.00
CONT_ASSIGN	1865	1	1	100.00
CONT_ASSIGN	1872	1	1	100.00
CONT_ASSIGN	1875	1	1	100.00
CONT_ASSIGN	1889	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1899	1	1	100.00
CONT_ASSIGN	1913	1	1	100.00
CONT_ASSIGN	1920	1	1	100.00
CONT_ASSIGN	1923	1	1	100.00
CONT_ASSIGN	1937	1	1	100.00
CONT_ASSIGN	1944	1	1	100.00
CONT_ASSIGN	1947	1	1	100.00
CONT_ASSIGN	1961	1	1	100.00
CONT_ASSIGN	1968	1	1	100.00
CONT_ASSIGN	1971	1	1	100.00
CONT_ASSIGN	1985	1	1	100.00
CONT_ASSIGN	1992	1	1	100.00
CONT_ASSIGN	1995	1	1	100.00
CONT_ASSIGN	2009	1	1	100.00
CONT_ASSIGN	2016	1	1	100.00
CONT_ASSIGN	2019	1	1	100.00
CONT_ASSIGN	2033	1	1	100.00
CONT_ASSIGN	2040	1	1	100.00
CONT_ASSIGN	2043	1	1	100.00
CONT_ASSIGN	2057	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2091	1	1	100.00
CONT_ASSIGN	2105	1	1	100.00
CONT_ASSIGN	2112	1	1	100.00
CONT_ASSIGN	2115	1	1	100.00
CONT_ASSIGN	2129	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2153	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2177	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2187	1	1	100.00
CONT_ASSIGN	2201	1	1	100.00
CONT_ASSIGN	2207	1	1	100.00
CONT_ASSIGN	2239	1	1	100.00
CONT_ASSIGN	2271	1	1	100.00
CONT_ASSIGN	2303	1	1	100.00
CONT_ASSIGN	2335	1	1	100.00
CONT_ASSIGN	2367	1	1	100.00
CONT_ASSIGN	2399	1	1	100.00
CONT_ASSIGN	2431	1	1	100.00
CONT_ASSIGN	2463	1	1	100.00
CONT_ASSIGN	2495	1	1	100.00
CONT_ASSIGN	2527	1	1	100.00
CONT_ASSIGN	2559	1	1	100.00
ALWAYS	2618	58	58	100.00
CONT_ASSIGN	2678	1	1	100.00
ALWAYS	2682	1	1	100.00
CONT_ASSIGN	2743	1	1	100.00
CONT_ASSIGN	2745	1	1	100.00
CONT_ASSIGN	2747	1	1	100.00
CONT_ASSIGN	2748	1	1	100.00
CONT_ASSIGN	2750	1	1	100.00
CONT_ASSIGN	2752	1	1	100.00
CONT_ASSIGN	2754	1	1	100.00
CONT_ASSIGN	2755	1	1	100.00
CONT_ASSIGN	2757	1	1	100.00
CONT_ASSIGN	2759	1	1	100.00
CONT_ASSIGN	2761	1	1	100.00
CONT_ASSIGN	2762	1	1	100.00
CONT_ASSIGN	2764	1	1	100.00
CONT_ASSIGN	2766	1	1	100.00
CONT_ASSIGN	2767	1	1	100.00
CONT_ASSIGN	2768	1	1	100.00
CONT_ASSIGN	2769	1	1	100.00
CONT_ASSIGN	2771	1	1	100.00
CONT_ASSIGN	2773	1	1	100.00
CONT_ASSIGN	2775	1	1	100.00
CONT_ASSIGN	2777	1	1	100.00
CONT_ASSIGN	2779	1	1	100.00
CONT_ASSIGN	2781	1	1	100.00
CONT_ASSIGN	2783	1	1	100.00
CONT_ASSIGN	2785	1	1	100.00
CONT_ASSIGN	2787	1	1	100.00
CONT_ASSIGN	2789	1	1	100.00
CONT_ASSIGN	2791	1	1	100.00
CONT_ASSIGN	2793	1	1	100.00
CONT_ASSIGN	2794	1	1	100.00
CONT_ASSIGN	2796	1	1	100.00
CONT_ASSIGN	2798	1	1	100.00
CONT_ASSIGN	2800	1	1	100.00
CONT_ASSIGN	2801	1	1	100.00
CONT_ASSIGN	2802	1	1	100.00
CONT_ASSIGN	2804	1	1	100.00
CONT_ASSIGN	2806	1	1	100.00
CONT_ASSIGN	2807	1	1	100.00
CONT_ASSIGN	2808	1	1	100.00
CONT_ASSIGN	2810	1	1	100.00
CONT_ASSIGN	2811	1	1	100.00
CONT_ASSIGN	2813	1	1	100.00
CONT_ASSIGN	2814	1	1	100.00
CONT_ASSIGN	2816	1	1	100.00
CONT_ASSIGN	2817	1	1	100.00
CONT_ASSIGN	2819	1	1	100.00
CONT_ASSIGN	2820	1	1	100.00
CONT_ASSIGN	2822	1	1	100.00
CONT_ASSIGN	2823	1	1	100.00
CONT_ASSIGN	2825	1	1	100.00
CONT_ASSIGN	2826	1	1	100.00
CONT_ASSIGN	2828	1	1	100.00
CONT_ASSIGN	2829	1	1	100.00
CONT_ASSIGN	2831	1	1	100.00
CONT_ASSIGN	2832	1	1	100.00
CONT_ASSIGN	2834	1	1	100.00
CONT_ASSIGN	2835	1	1	100.00
CONT_ASSIGN	2837	1	1	100.00
CONT_ASSIGN	2838	1	1	100.00
CONT_ASSIGN	2840	1	1	100.00
CONT_ASSIGN	2841	1	1	100.00
CONT_ASSIGN	2843	1	1	100.00
CONT_ASSIGN	2844	1	1	100.00
CONT_ASSIGN	2846	1	1	100.00
CONT_ASSIGN	2847	1	1	100.00
CONT_ASSIGN	2849	1	1	100.00
CONT_ASSIGN	2850	1	1	100.00
CONT_ASSIGN	2852	1	1	100.00
CONT_ASSIGN	2853	1	1	100.00
CONT_ASSIGN	2855	1	1	100.00
CONT_ASSIGN	2856	1	1	100.00
CONT_ASSIGN	2858	1	1	100.00
CONT_ASSIGN	2859	1	1	100.00
CONT_ASSIGN	2861	1	1	100.00
CONT_ASSIGN	2862	1	1	100.00
CONT_ASSIGN	2864	1	1	100.00
CONT_ASSIGN	2865	1	1	100.00
CONT_ASSIGN	2867	1	1	100.00
CONT_ASSIGN	2868	1	1	100.00
CONT_ASSIGN	2870	1	1	100.00
CONT_ASSIGN	2871	1	1	100.00
CONT_ASSIGN	2873	1	1	100.00
CONT_ASSIGN	2874	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2877	1	1	100.00
CONT_ASSIGN	2879	1	1	100.00
CONT_ASSIGN	2880	1	1	100.00
CONT_ASSIGN	2882	1	1	100.00
CONT_ASSIGN	2883	1	1	100.00
CONT_ASSIGN	2885	1	1	100.00
CONT_ASSIGN	2886	1	1	100.00
CONT_ASSIGN	2888	1	1	100.00
CONT_ASSIGN	2889	1	1	100.00
CONT_ASSIGN	2891	1	1	100.00
CONT_ASSIGN	2892	1	1	100.00
CONT_ASSIGN	2894	1	1	100.00
CONT_ASSIGN	2895	1	1	100.00
CONT_ASSIGN	2897	1	1	100.00
CONT_ASSIGN	2898	1	1	100.00
CONT_ASSIGN	2900	1	1	100.00
CONT_ASSIGN	2901	1	1	100.00
CONT_ASSIGN	2903	1	1	100.00
CONT_ASSIGN	2904	1	1	100.00
CONT_ASSIGN	2906	1	1	100.00
CONT_ASSIGN	2907	1	1	100.00
CONT_ASSIGN	2909	1	1	100.00
CONT_ASSIGN	2910	1	1	100.00
CONT_ASSIGN	2912	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2915	1	1	100.00
CONT_ASSIGN	2916	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2919	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
CONT_ASSIGN	2922	1	1	100.00
CONT_ASSIGN	2924	1	1	100.00
CONT_ASSIGN	2925	1	1	100.00
CONT_ASSIGN	2927	1	1	100.00
CONT_ASSIGN	2928	1	1	100.00
CONT_ASSIGN	2930	1	1	100.00
CONT_ASSIGN	2931	1	1	100.00
CONT_ASSIGN	2933	1	1	100.00
CONT_ASSIGN	2934	1	1	100.00
CONT_ASSIGN	2936	1	1	100.00
CONT_ASSIGN	2937	1	1	100.00
CONT_ASSIGN	2939	1	1	100.00
CONT_ASSIGN	2940	1	1	100.00
CONT_ASSIGN	2942	1	1	100.00
CONT_ASSIGN	2943	1	1	100.00
CONT_ASSIGN	2945	1	1	100.00
ALWAYS	2949	58	58	100.00
ALWAYS	3011	87	87	100.00
ALWAYS	3280	3	3	100.00
ALWAYS	3288	3	3	100.00
CONT_ASSIGN	3296	1	1	100.00
CONT_ASSIGN	3299	1	1	100.00
CONT_ASSIGN	3314	1	1	100.00
CONT_ASSIGN	3331	1	1	100.00
CONT_ASSIGN	3339	1	1	100.00
CONT_ASSIGN	3340	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
77	1	1
78	1	1
79	1	1
80	1	1
			MISSING_ELSE
86	1	1
104	1	1
105	1	1
107	1	1
108	1	1
109	1	1
110	1	1
136	1	1
143	1	1
144	1	1
			MISSING_ELSE
174	1	1
175	1	1
550	1	1
565	1	1
581	1	1
597	1	1
603	1	1
618	1	1
634	1	1
667	1	1
703	1	1
740	1	1
777	1	1
814	1	1
851	1	1
888	1	1
925	1	1
962	1	1
999	1	1
1036	1	1
1073	1	1
1110	1	1
1116	1	1
1131	1	1
1147	1	1
1163	1	1
1291	1	1
1378	1	1
1419	1	1
1433	1	1
1440	1	1
1443	1	1
1457	1	1
1464	1	1
1467	1	1
1481	1	1
1488	1	1
1491	1	1
1505	1	1
1512	1	1
1515	1	1
1529	1	1
1536	1	1
1539	1	1
1553	1	1
1560	1	1
1563	1	1
1577	1	1
1584	1	1
1587	1	1
1601	1	1
1608	1	1
1611	1	1
1625	1	1
1632	1	1
1635	1	1
1649	1	1
1656	1	1
1659	1	1
1673	1	1
1680	1	1
1683	1	1
1697	1	1
1704	1	1
1707	1	1
1721	1	1
1728	1	1
1731	1	1
1745	1	1
1752	1	1
1755	1	1
1769	1	1
1776	1	1
1779	1	1
1793	1	1
1800	1	1
1803	1	1
1817	1	1
1824	1	1
1827	1	1
1841	1	1
1848	1	1
1851	1	1
1865	1	1
1872	1	1
1875	1	1
1889	1	1
1896	1	1
1899	1	1
1913	1	1
1920	1	1
1923	1	1
1937	1	1
1944	1	1
1947	1	1
1961	1	1
1968	1	1
1971	1	1
1985	1	1
1992	1	1
1995	1	1
2009	1	1
2016	1	1
2019	1	1
2033	1	1
2040	1	1
2043	1	1
2057	1	1
2064	1	1
2067	1	1
2081	1	1
2088	1	1
2091	1	1
2105	1	1
2112	1	1
2115	1	1
2129	1	1
2136	1	1
2139	1	1
2153	1	1
2160	1	1
2163	1	1
2177	1	1
2184	1	1
2187	1	1
2201	1	1
2207	1	1
2239	1	1
2271	1	1
2303	1	1
2335	1	1
2367	1	1
2399	1	1
2431	1	1
2463	1	1
2495	1	1
2527	1	1
2559	1	1
2618	1	1
2619	1	1
2620	1	1
2621	1	1
2622	1	1
2623	1	1
2624	1	1
2625	1	1
2626	1	1
2627	1	1
2628	1	1
2629	1	1
2630	1	1
2631	1	1
2632	1	1
2633	1	1
2634	1	1
2635	1	1
2636	1	1
2637	1	1
2638	1	1
2639	1	1
2640	1	1
2641	1	1
2642	1	1
2643	1	1
2644	1	1
2645	1	1
2646	1	1
2647	1	1
2648	1	1
2649	1	1
2650	1	1
2651	1	1
2652	1	1
2653	1	1
2654	1	1
2655	1	1
2656	1	1
2657	1	1
2658	1	1
2659	1	1
2660	1	1
2661	1	1
2662	1	1
2663	1	1
2664	1	1
2665	1	1
2666	1	1
2667	1	1
2668	1	1
2669	1	1
2670	1	1
2671	1	1
2672	1	1
2673	1	1
2674	1	1
2675	1	1
2678	1	1
2682	1	1
2743	1	1
2745	1	1
2747	1	1
2748	1	1
2750	1	1
2752	1	1
2754	1	1
2755	1	1
2757	1	1
2759	1	1
2761	1	1
2762	1	1
2764	1	1
2766	1	1
2767	1	1
2768	1	1
2769	1	1
2771	1	1
2773	1	1
2775	1	1
2777	1	1
2779	1	1
2781	1	1
2783	1	1
2785	1	1
2787	1	1
2789	1	1
2791	1	1
2793	1	1
2794	1	1
2796	1	1
2798	1	1
2800	1	1
2801	1	1
2802	1	1
2804	1	1
2806	1	1
2807	1	1
2808	1	1
2810	1	1
2811	1	1
2813	1	1
2814	1	1
2816	1	1
2817	1	1
2819	1	1
2820	1	1
2822	1	1
2823	1	1
2825	1	1
2826	1	1
2828	1	1
2829	1	1
2831	1	1
2832	1	1
2834	1	1
2835	1	1
2837	1	1
2838	1	1
2840	1	1
2841	1	1
2843	1	1
2844	1	1
2846	1	1
2847	1	1
2849	1	1
2850	1	1
2852	1	1
2853	1	1
2855	1	1
2856	1	1
2858	1	1
2859	1	1
2861	1	1
2862	1	1
2864	1	1
2865	1	1
2867	1	1
2868	1	1
2870	1	1
2871	1	1
2873	1	1
2874	1	1
2876	1	1
2877	1	1
2879	1	1
2880	1	1
2882	1	1
2883	1	1
2885	1	1
2886	1	1
2888	1	1
2889	1	1
2891	1	1
2892	1	1
2894	1	1
2895	1	1
2897	1	1
2898	1	1
2900	1	1
2901	1	1
2903	1	1
2904	1	1
2906	1	1
2907	1	1
2909	1	1
2910	1	1
2912	1	1
2913	1	1
2915	1	1
2916	1	1
2918	1	1
2919	1	1
2921	1	1
2922	1	1
2924	1	1
2925	1	1
2927	1	1
2928	1	1
2930	1	1
2931	1	1
2933	1	1
2934	1	1
2936	1	1
2937	1	1
2939	1	1
2940	1	1
2942	1	1
2943	1	1
2945	1	1
2949	1	1
2950	1	1
2951	1	1
2952	1	1
2953	1	1
2954	1	1
2955	1	1
2956	1	1
2957	1	1
2958	1	1
2959	1	1
2960	1	1
2961	1	1
2962	1	1
2963	1	1
2964	1	1
2965	1	1
2966	1	1
2967	1	1
2968	1	1
2969	1	1
2970	1	1
2971	1	1
2972	1	1
2973	1	1
2974	1	1
2975	1	1
2976	1	1
2977	1	1
2978	1	1
2979	1	1
2980	1	1
2981	1	1
2982	1	1
2983	1	1
2984	1	1
2985	1	1
2986	1	1
2987	1	1
2988	1	1
2989	1	1
2990	1	1
2991	1	1
2992	1	1
2993	1	1
2994	1	1
2995	1	1
2996	1	1
2997	1	1
2998	1	1
2999	1	1
3000	1	1
3001	1	1
3002	1	1
3003	1	1
3004	1	1
3005	1	1
3006	1	1
3011	1	1
3012	1	1
3014	1	1
3015	1	1
3016	1	1
3020	1	1
3021	1	1
3022	1	1
3026	1	1
3027	1	1
3028	1	1
3032	1	1
3033	1	1
3037	1	1
3041	1	1
3042	1	1
3043	1	1
3044	1	1
3045	1	1
3046	1	1
3047	1	1
3048	1	1
3049	1	1
3050	1	1
3051	1	1
3052	1	1
3056	1	1
3057	1	1
3058	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3073	1	1
3074	1	1
3078	1	1
3082	1	1
3086	1	1
3090	1	1
3094	1	1
3098	1	1
3102	1	1
3106	1	1
3110	1	1
3114	1	1
3118	1	1
3122	1	1
3126	1	1
3130	1	1
3134	1	1
3138	1	1
3142	1	1
3146	1	1
3150	1	1
3154	1	1
3158	1	1
3162	1	1
3166	1	1
3170	1	1
3174	1	1
3178	1	1
3182	1	1
3186	1	1
3190	1	1
3194	1	1
3198	1	1
3202	1	1
3206	1	1
3210	1	1
3214	1	1
3218	1	1
3222	1	1
3226	1	1
3230	1	1
3234	1	1
3238	1	1
3242	1	1
3246	1	1
3250	1	1
3254	1	1
3258	1	1
3262	1	1
3266	1	1
3280	1	1
3281	1	1
3283	1	1
3288	1	1
3289	1	1
3291	1	1
3296	1	1
3299	1	1
3314	1	1
3331	1	1
3339	1	1
3340	1	1

---

Cond Coverage for Module : kmac_reg_top

	Total	Covered	Percent
Conditions	741	737	99.46
Logical	741	737	99.46
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
67-2682	100.00
2682-3296	98.74

---

Branch Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
Branches		72	72	100.00
TERNARY	2678	2	2	100.00
IF	77	3	3	100.00
TERNARY	136	3	3	100.00
IF	143	2	2	100.00
CASE	3012	58	58	100.00
IF	3280	2	2	100.00
IF	3288	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2678	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if ((!rst_ni))
-2-:	79	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	((tl_i.a_address[(AW - 1):0] inside {[1024:1535]})) ? 
-2-:	136	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T125,T126,T127
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3012	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T2,T3,T4
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T2,T3,T4
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T2,T3,T4
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3280	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3288	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	314432895	0	0
reAfterRv	2147483647	314432895	0	0
rePulse	2147483647	208322627	0	0
wePulse	2147483647	106110268	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	314432895	0	0
T1	75770	870	0	0
T2	1968	22	0	0
T3	121581	87400	0	0
T4	15200	1449	0	0
T5	16471	1212	0	0
T6	617009	635785	0	0
T7	122117	25695	0	0
T12	158671	79967	0	0
T13	114620	342203	0	0
T14	678445	677894	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	314432895	0	0
T1	75770	870	0	0
T2	1968	22	0	0
T3	121581	87400	0	0
T4	15200	1449	0	0
T5	16471	1212	0	0
T6	617009	635785	0	0
T7	122117	25695	0	0
T12	158671	79967	0	0
T13	114620	342203	0	0
T14	678445	677894	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208322627	0	0
T1	75770	61	0	0
T2	1968	1	0	0
T3	121581	55417	0	0
T4	15200	645	0	0
T5	16471	483	0	0
T6	617009	419701	0	0
T7	122117	17827	0	0
T12	158671	49635	0	0
T13	114620	226391	0	0
T14	678445	449167	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106110268	0	0
T1	75770	809	0	0
T2	1968	21	0	0
T3	121581	31983	0	0
T4	15200	804	0	0
T5	16471	729	0	0
T6	617009	216084	0	0
T7	122117	7868	0	0
T12	158671	30332	0	0
T13	114620	115812	0	0
T14	678445	228727	0	0