Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	766497	0	0
entropy_period_rd_A	2147483647	2153	0	0
intr_enable_rd_A	2147483647	2953	0	0
prefix_0_rd_A	2147483647	2145	0	0
prefix_10_rd_A	2147483647	2008	0	0
prefix_1_rd_A	2147483647	2191	0	0
prefix_2_rd_A	2147483647	2221	0	0
prefix_3_rd_A	2147483647	2231	0	0
prefix_4_rd_A	2147483647	2089	0	0
prefix_5_rd_A	2147483647	2103	0	0
prefix_6_rd_A	2147483647	2191	0	0
prefix_7_rd_A	2147483647	2320	0	0
prefix_8_rd_A	2147483647	2265	0	0
prefix_9_rd_A	2147483647	2335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	766497	0	0
T41	197999	0	0	0
T64	171926	26687	0	0
T80	0	73382	0	0
T81	0	20606	0	0
T132	0	71669	0	0
T133	0	67767	0	0
T134	0	27868	0	0
T135	0	62158	0	0
T136	0	30818	0	0
T137	0	57072	0	0
T138	0	22137	0	0
T139	253368	0	0	0
T140	110811	0	0	0
T141	86912	0	0	0
T142	6695	0	0	0
T143	1706	0	0	0
T144	1795	0	0	0
T145	9816	0	0	0
T146	263015	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2153	0	0
T81	647515	69	0	0
T96	0	82	0	0
T99	0	79	0	0
T112	0	3	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	92	0	0
T153	0	63	0	0
T154	0	17	0	0
T155	0	247	0	0
T156	0	209	0	0
T157	0	9	0	0
T158	200321	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2953	0	0
T81	647515	57	0	0
T96	0	71	0	0
T99	0	80	0	0
T112	0	17	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T129	0	11	0	0
T136	0	79	0	0
T153	0	83	0	0
T154	0	45	0	0
T155	0	364	0	0
T156	0	179	0	0
T158	200321	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2145	0	0
T81	647515	58	0	0
T96	0	38	0	0
T99	0	56	0	0
T112	0	7	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	69	0	0
T153	0	72	0	0
T154	0	27	0	0
T155	0	466	0	0
T156	0	210	0	0
T157	0	5	0	0
T158	200321	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T81	647515	59	0	0
T96	0	30	0	0
T99	0	62	0	0
T112	0	15	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	48	0	0
T153	0	85	0	0
T154	0	27	0	0
T155	0	414	0	0
T156	0	196	0	0
T157	0	3	0	0
T158	200321	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T81	647515	44	0	0
T96	0	60	0	0
T99	0	59	0	0
T112	0	1	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	76	0	0
T153	0	90	0	0
T154	0	39	0	0
T155	0	524	0	0
T156	0	193	0	0
T157	0	1	0	0
T158	200321	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2221	0	0
T81	647515	66	0	0
T96	0	49	0	0
T99	0	59	0	0
T112	0	15	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	66	0	0
T153	0	72	0	0
T154	0	53	0	0
T155	0	363	0	0
T156	0	215	0	0
T158	200321	0	0	0
T159	0	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2231	0	0
T81	647515	63	0	0
T96	0	59	0	0
T99	0	43	0	0
T112	0	13	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	87	0	0
T153	0	62	0	0
T154	0	38	0	0
T155	0	432	0	0
T156	0	203	0	0
T157	0	4	0	0
T158	200321	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2089	0	0
T81	647515	54	0	0
T96	0	68	0	0
T99	0	50	0	0
T112	0	15	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	75	0	0
T153	0	37	0	0
T154	0	32	0	0
T155	0	427	0	0
T156	0	216	0	0
T157	0	2	0	0
T158	200321	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2103	0	0
T81	647515	72	0	0
T96	0	56	0	0
T99	0	62	0	0
T112	0	8	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	51	0	0
T153	0	35	0	0
T154	0	35	0	0
T155	0	449	0	0
T156	0	208	0	0
T158	200321	0	0	0
T159	0	2	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T81	647515	77	0	0
T96	0	75	0	0
T99	0	52	0	0
T112	0	2	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	98	0	0
T153	0	59	0	0
T154	0	33	0	0
T155	0	441	0	0
T156	0	217	0	0
T157	0	6	0	0
T158	200321	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2320	0	0
T81	647515	59	0	0
T96	0	51	0	0
T99	0	45	0	0
T112	0	15	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	67	0	0
T153	0	98	0	0
T154	0	19	0	0
T155	0	466	0	0
T156	0	242	0	0
T157	0	2	0	0
T158	200321	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2265	0	0
T81	647515	74	0	0
T96	0	65	0	0
T99	0	59	0	0
T112	0	16	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	79	0	0
T153	0	83	0	0
T154	0	33	0	0
T155	0	450	0	0
T156	0	212	0	0
T157	0	3	0	0
T158	200321	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2335	0	0
T81	647515	64	0	0
T96	0	46	0	0
T99	0	49	0	0
T112	0	9	0	0
T117	115903	0	0	0
T118	650201	0	0	0
T119	84507	0	0	0
T120	135008	0	0	0
T121	257842	0	0	0
T122	787435	0	0	0
T123	385935	0	0	0
T124	69287	0	0	0
T136	0	100	0	0
T153	0	80	0	0
T154	0	47	0	0
T155	0	437	0	0
T156	0	229	0	0
T157	0	3	0	0
T158	200321	0	0	0