Group : kmac_env_pkg::app_cg_wrap::app_cg
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Group : kmac_env_pkg::app_cg_wrap::app_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
94.44 90.74 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
AppLc_cg 88.89 1 100 1 64 64
AppRom_cg 88.89 1 100 1 64 64
AppKeymgr_cg 94.44 1 100 1 64 64




Group Instance : AppLc_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
88.89 1 100 1 64 64




Summary for Group Instance AppLc_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 2 0 2 100.00


Variables for Group Instance AppLc_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
app_err 2 1 1 50.00 100 1 1 2
data_strb 8 0 8 100.00 100 1 1 0
done 2 0 2 100.00 100 1 1 2
in_keccak_rounds 2 1 1 50.00 100 1 1 2
single_data_beat 2 0 2 100.00 100 1 1 2


Crosses for Group Instance AppLc_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
partial_data_on_last_beat 1 0 1 100.00 100 1 1 0
done_in_keccak_rounds 1 0 1 100.00 100 1 1 0



Group Instance : AppRom_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
88.89 1 100 1 64 64




Summary for Group Instance AppRom_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 2 0 2 100.00


Variables for Group Instance AppRom_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
app_err 2 1 1 50.00 100 1 1 2
data_strb 8 0 8 100.00 100 1 1 0
done 2 0 2 100.00 100 1 1 2
in_keccak_rounds 2 1 1 50.00 100 1 1 2
single_data_beat 2 0 2 100.00 100 1 1 2


Crosses for Group Instance AppRom_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
partial_data_on_last_beat 1 0 1 100.00 100 1 1 0
done_in_keccak_rounds 1 0 1 100.00 100 1 1 0



Group Instance : AppKeymgr_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
94.44 1 100 1 64 64




Summary for Group Instance AppKeymgr_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 1 15 93.75
Crosses 2 0 2 100.00


Variables for Group Instance AppKeymgr_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
app_err 2 0 2 100.00 100 1 1 2
data_strb 8 0 8 100.00 100 1 1 0
done 2 0 2 100.00 100 1 1 2
in_keccak_rounds 2 1 1 50.00 100 1 1 2
single_data_beat 2 0 2 100.00 100 1 1 2


Crosses for Group Instance AppKeymgr_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
partial_data_on_last_beat 1 0 1 100.00 100 1 1 0
done_in_keccak_rounds 1 0 1 100.00 100 1 1 0


Summary for Variable app_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for app_err

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 163783 1 T2 1821 T4 112 T7 922



Summary for Variable data_strb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for data_strb

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 82220 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
full_data_beat 62319 1 T2 1795 T4 111 T7 909
seven_bytes 2761 1 T14 24 T35 4 T22 1
six_bytes 2833 1 T14 23 T35 3 T8 1
five_bytes 2762 1 T14 23 T35 3 T8 1
four_bytes 2738 1 T14 23 T35 4 T22 2
three_bytes 2667 1 T14 14 T35 4 T22 1
two_bytes 2742 1 T14 19 T35 4 T23 55
one_byte 2741 1 T14 20 T35 1 T23 87



Summary for Variable done

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for done

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 160577 1 T2 1769 T4 110 T7 896
auto[1] 3206 1 T2 52 T4 2 T7 26



Summary for Variable in_keccak_rounds

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for in_keccak_rounds

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 163783 1 T2 1821 T4 112 T7 922



Summary for Variable single_data_beat

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for single_data_beat

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 163775 1 T2 1821 T4 112 T7 922
auto[1] 8 1 T161 3 T162 1 T163 1



Summary for Cross partial_data_on_last_beat

Samples crossed: done data_strb
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for partial_data_on_last_beat

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 1136 1 T2 26 T4 1 T7 13



Summary for Cross done_in_keccak_rounds

Samples crossed: done in_keccak_rounds
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for done_in_keccak_rounds

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 3206 1 T2 52 T4 2 T7 26


Summary for Variable app_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for app_err

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 169855 1 T2 1543 T4 225 T7 736



Summary for Variable data_strb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for data_strb

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 83567 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
full_data_beat 66373 1 T2 1521 T4 220 T7 727
seven_bytes 2796 1 T14 25 T35 8 T8 8
six_bytes 2782 1 T14 29 T35 5 T8 16
five_bytes 2826 1 T14 23 T35 7 T8 9
four_bytes 2917 1 T14 34 T35 6 T8 14
three_bytes 2840 1 T14 20 T35 6 T8 18
two_bytes 2838 1 T14 25 T35 8 T8 12
one_byte 2916 1 T14 36 T35 9 T8 15



Summary for Variable done

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for done

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 166577 1 T2 1499 T4 215 T7 718
auto[1] 3278 1 T2 44 T4 10 T7 18



Summary for Variable in_keccak_rounds

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for in_keccak_rounds

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 169855 1 T2 1543 T4 225 T7 736



Summary for Variable single_data_beat

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for single_data_beat

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 169844 1 T2 1543 T4 225 T7 736
auto[1] 11 1 T68 1 T25 1 T164 1



Summary for Cross partial_data_on_last_beat

Samples crossed: done data_strb
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for partial_data_on_last_beat

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 1173 1 T2 22 T4 5 T7 9



Summary for Cross done_in_keccak_rounds

Samples crossed: done in_keccak_rounds
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for done_in_keccak_rounds

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 3278 1 T2 44 T4 10 T7 18


Summary for Variable app_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for app_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322120 1 T2 1872 T4 148 T7 952
auto[1] 471 1 T48 59 T49 32 T50 32



Summary for Variable data_strb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for data_strb

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 162301 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
full_data_beat 121827 1 T2 1836 T4 146 T7 937
seven_bytes 5484 1 T14 10 T35 13 T8 16
six_bytes 5531 1 T14 12 T35 16 T8 16
five_bytes 5512 1 T14 10 T35 18 T8 23
four_bytes 5479 1 T14 4 T35 14 T8 19
three_bytes 5593 1 T14 7 T35 15 T8 25
two_bytes 5525 1 T14 8 T35 9 T8 17
one_byte 5339 1 T14 10 T35 11 T8 13



Summary for Variable done

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for done

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 316279 1 T2 1800 T4 144 T7 922
auto[1] 6312 1 T2 72 T4 4 T7 30



Summary for Variable in_keccak_rounds

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for in_keccak_rounds

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322591 1 T2 1872 T4 148 T7 952



Summary for Variable single_data_beat

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for single_data_beat

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322564 1 T2 1872 T4 148 T7 952
auto[1] 27 1 T14 1 T23 1 T165 1



Summary for Cross partial_data_on_last_beat

Samples crossed: done data_strb
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for partial_data_on_last_beat

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 2243 1 T2 36 T4 2 T7 15



Summary for Cross done_in_keccak_rounds

Samples crossed: done in_keccak_rounds
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for done_in_keccak_rounds

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 6312 1 T2 72 T4 4 T7 30

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