Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259534905	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184809330

1

T1

1

T2

78581

T3

290505

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230105781	1			T1	1		T2	105233		T3	346900
values[0x0]	102895729	1			T1	2		T2	19800		T3	115887
values[0x1]	111342725	1			T1	1		T2	21191		T3	116921

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201608971	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

242735264

1

T1

1

T2

95956

T3

365365

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2091590	1			T2	530		T3	2274		T4	35
valid_sources[0x01]	1308664	1			T2	613		T3	2233		T4	24
valid_sources[0x02]	1312169	1			T2	518		T3	2267		T4	38
valid_sources[0x03]	1302824	1			T2	509		T3	2140		T4	41
valid_sources[0x04]	1305129	1			T2	665		T3	2191		T4	24
valid_sources[0x05]	2207202	1			T2	648		T3	2209		T4	33
valid_sources[0x06]	3654740	1			T2	549		T3	2162		T4	36
valid_sources[0x07]	1304784	1			T2	547		T3	2254		T4	33
valid_sources[0x08]	3676485	1			T2	607		T3	2319		T4	39
valid_sources[0x09]	1767782	1			T2	569		T3	2241		T4	37
valid_sources[0x0a]	1312338	1			T2	615		T3	2261		T4	32
valid_sources[0x0b]	1298485	1			T2	602		T3	2184		T4	25
valid_sources[0x0c]	1308023	1			T2	586		T3	2228		T4	34
valid_sources[0x0d]	2224316	1			T2	553		T3	2314		T4	26
valid_sources[0x0e]	1307936	1			T2	565		T3	2185		T4	39
valid_sources[0x0f]	1306182	1			T2	566		T3	2314		T4	36
valid_sources[0x10]	1302729	1			T2	584		T3	2246		T4	32
valid_sources[0x11]	2371740	1			T2	579		T3	2245		T4	37
valid_sources[0x12]	1302112	1			T2	531		T3	2248		T4	36
valid_sources[0x13]	2655518	1			T2	580		T3	2276		T4	38
valid_sources[0x14]	1748200	1			T2	620		T3	2329		T4	33
valid_sources[0x15]	1306059	1			T2	602		T3	2225		T4	24
valid_sources[0x16]	3262644	1			T2	594		T3	2146		T4	35
valid_sources[0x17]	1310178	1			T2	586		T3	2226		T4	34
valid_sources[0x18]	1298429	1			T2	562		T3	2303		T4	37
valid_sources[0x19]	1528316	1			T2	488		T3	2342		T4	28
valid_sources[0x1a]	1294161	1			T2	599		T3	2302		T4	31
valid_sources[0x1b]	2629878	1			T2	569		T3	2226		T4	31
valid_sources[0x1c]	1299953	1			T2	631		T3	2230		T4	29
valid_sources[0x1d]	1423472	1			T2	586		T3	2278		T4	32
valid_sources[0x1e]	1306896	1			T2	578		T3	2307		T4	24
valid_sources[0x1f]	1303488	1			T2	549		T3	2227		T4	37
valid_sources[0x20]	2163394	1			T2	553		T3	2203		T4	35
valid_sources[0x21]	3296412	1			T2	542		T3	2293		T4	29
valid_sources[0x22]	4149459	1			T2	551		T3	2185		T4	36
valid_sources[0x23]	1307189	1			T2	530		T3	2252		T4	30
valid_sources[0x24]	1303985	1			T2	604		T3	2257		T4	32
valid_sources[0x25]	2224090	1			T2	557		T3	2321		T4	32
valid_sources[0x26]	4083089	1			T2	560		T3	2182		T4	32
valid_sources[0x27]	1327877	1			T2	574		T3	2208		T4	29
valid_sources[0x28]	1302362	1			T2	570		T3	2175		T4	32
valid_sources[0x29]	1518815	1			T2	535		T3	2357		T4	35
valid_sources[0x2a]	2171659	1			T2	577		T3	2193		T4	33
valid_sources[0x2b]	1409938	1			T2	633		T3	2419		T4	28
valid_sources[0x2c]	1303108	1			T2	559		T3	2299		T4	39
valid_sources[0x2d]	1302784	1			T2	575		T3	2095		T4	35
valid_sources[0x2e]	1302919	1			T2	534		T3	2302		T4	38
valid_sources[0x2f]	1455045	1			T2	517		T3	2293		T4	36
valid_sources[0x30]	3254069	1			T2	563		T3	2200		T4	31
valid_sources[0x31]	3117917	1			T2	573		T3	2295		T4	26
valid_sources[0x32]	1301447	1			T2	523		T3	2182		T4	35
valid_sources[0x33]	1454273	1			T2	574		T3	2356		T4	30
valid_sources[0x34]	1307423	1			T2	623		T3	2378		T4	37
valid_sources[0x35]	1304236	1			T2	552		T3	2306		T4	39
valid_sources[0x36]	1300173	1			T2	524		T3	2179		T4	23
valid_sources[0x37]	3273941	1			T2	642		T3	2249		T4	36
valid_sources[0x38]	1364704	1			T2	626		T3	2245		T4	33
valid_sources[0x39]	1301019	1			T2	526		T3	2240		T4	41
valid_sources[0x3a]	3286939	1			T2	560		T3	2370		T4	36
valid_sources[0x3b]	3630813	1			T2	573		T3	2272		T4	36
valid_sources[0x3c]	1323263	1			T2	548		T3	2368		T4	29
valid_sources[0x3d]	2176161	1			T2	639		T3	2271		T4	30
valid_sources[0x3e]	1305513	1			T2	600		T3	2243		T4	27
valid_sources[0x3f]	1308566	1			T2	539		T3	2300		T4	25
valid_sources[0x40]	3681535	1			T2	587		T3	2317		T4	39
valid_sources[0x41]	1312243	1			T2	518		T3	2237		T4	26
valid_sources[0x42]	2471044	1			T2	557		T3	2192		T4	38
valid_sources[0x43]	2154016	1			T2	541		T3	2242		T4	25
valid_sources[0x44]	4558171	1			T2	522		T3	2224		T4	31
valid_sources[0x45]	1303656	1			T2	595		T3	2258		T4	27
valid_sources[0x46]	1959793	1			T2	602		T3	2345		T4	29
valid_sources[0x47]	3285607	1			T2	625		T3	2205		T4	33
valid_sources[0x48]	2145208	1			T2	536		T3	2352		T4	28
valid_sources[0x49]	1306165	1			T2	581		T3	2348		T4	31
valid_sources[0x4a]	1771724	1			T2	523		T3	2225		T4	33
valid_sources[0x4b]	1521762	1			T2	563		T3	2314		T4	33
valid_sources[0x4c]	1306151	1			T2	606		T3	2232		T4	28
valid_sources[0x4d]	2215798	1			T2	614		T3	2270		T4	33
valid_sources[0x4e]	1302951	1			T2	549		T3	2235		T4	34
valid_sources[0x4f]	1303025	1			T2	542		T3	2417		T4	35
valid_sources[0x50]	1464694	1			T2	553		T3	2250		T4	33
valid_sources[0x51]	1307076	1			T2	573		T3	2253		T4	36
valid_sources[0x52]	2149517	1			T2	663		T3	2233		T4	33
valid_sources[0x53]	1297206	1			T2	603		T3	2298		T4	31
valid_sources[0x54]	1303374	1			T2	529		T3	2214		T4	36
valid_sources[0x55]	1304380	1			T2	593		T3	2264		T4	35
valid_sources[0x56]	1299800	1			T2	544		T3	2126		T4	33
valid_sources[0x57]	1305499	1			T2	571		T3	2210		T4	23
valid_sources[0x58]	1325940	1			T2	582		T3	2311		T4	29
valid_sources[0x59]	1301147	1			T2	584		T3	2352		T4	28
valid_sources[0x5a]	1297687	1			T2	601		T3	2417		T4	41
valid_sources[0x5b]	2234953	1			T2	578		T3	2306		T4	23
valid_sources[0x5c]	2355421	1			T2	600		T3	2201		T4	27
valid_sources[0x5d]	1701063	1			T2	529		T3	2294		T4	30
valid_sources[0x5e]	1410101	1			T2	565		T3	2292		T4	23
valid_sources[0x5f]	1306942	1			T2	640		T3	2176		T4	41
valid_sources[0x60]	4189725	1			T2	541		T3	2317		T4	37
valid_sources[0x61]	3642409	1			T2	586		T3	2219		T4	33
valid_sources[0x62]	1484383	1			T2	569		T3	2274		T4	31
valid_sources[0x63]	3284588	1			T2	602		T3	2231		T4	26
valid_sources[0x64]	1312787	1			T2	561		T3	2244		T4	26
valid_sources[0x65]	2200800	1			T2	566		T3	2273		T4	32
valid_sources[0x66]	2298749	1			T2	569		T3	2348		T4	39
valid_sources[0x67]	1610282	1			T2	532		T3	2274		T4	40
valid_sources[0x68]	3036249	1			T2	574		T3	2252		T4	34
valid_sources[0x69]	1312396	1			T2	564		T3	2252		T4	34
valid_sources[0x6a]	1311700	1			T2	615		T3	2266		T4	26
valid_sources[0x6b]	1307581	1			T2	520		T3	2300		T4	26
valid_sources[0x6c]	1763061	1			T2	562		T3	2235		T4	38
valid_sources[0x6d]	2136749	1			T2	607		T3	2274		T4	37
valid_sources[0x6e]	1309520	1			T2	473		T3	2186		T4	30
valid_sources[0x6f]	4344039	1			T2	597		T3	2313		T4	36
valid_sources[0x70]	1303222	1			T2	603		T3	2252		T4	40
valid_sources[0x71]	1363430	1			T2	562		T3	2156		T4	32
valid_sources[0x72]	1303888	1			T2	589		T3	2131		T4	33
valid_sources[0x73]	1369068	1			T2	562		T3	2146		T4	29
valid_sources[0x74]	2566866	1			T2	606		T3	2209		T4	24
valid_sources[0x75]	2851754	1			T2	567		T3	2364		T4	38
valid_sources[0x76]	1299335	1			T2	520		T3	2151		T4	31
valid_sources[0x77]	2208635	1			T2	558		T3	2212		T4	34
valid_sources[0x78]	1307627	1			T2	500		T3	2363		T4	28
valid_sources[0x79]	1954883	1			T2	550		T3	2288		T4	31
valid_sources[0x7a]	1299454	1			T2	619		T3	2318		T4	24
valid_sources[0x7b]	1302594	1			T2	551		T3	2110		T4	23
valid_sources[0x7c]	1436263	1			T2	495		T3	2286		T4	36
valid_sources[0x7d]	1384159	1			T2	591		T3	2408		T4	30
valid_sources[0x7e]	2031719	1			T2	618		T3	2172		T4	44
valid_sources[0x7f]	3667333	1			T2	570		T3	2252		T4	31
valid_sources[0x80]	1306967	1			T2	509		T3	2341		T4	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71329319

1

T2

56220

T3

61131

T4

49140

values[0x0]

all_enables

biggest_size

60960065

1

T2

11915

T3

114404

T4

13479

values[0x1]

all_enables

biggest_size

52519946

1

T1

1

T2

10446

T3

114970