SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[kmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 316971104 | 1 | T1 | 4 | T2 | 82061 | T3 | 299228 | ||||
auto[1] | 131353331 | 1 | T2 | 64163 | T3 | 280480 | T4 | 57701 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 448324243 | 1 | T1 | 4 | T2 | 146224 | T3 | 579708 | ||||
values[1] | 16 | 1 | T114 | 2 | T166 | 1 | T167 | 1 | ||||
values[2] | 6 | 1 | T114 | 1 | T116 | 1 | T168 | 2 | ||||
values[3] | 100 | 1 | T114 | 5 | T115 | 5 | T116 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 448324269 | 1 | T1 | 4 | T2 | 146224 | T3 | 579708 | ||||
values[1] | 17 | 1 | T114 | 1 | T115 | 1 | T166 | 1 | ||||
values[2] | 2 | 1 | T114 | 1 | T167 | 1 | - | - | ||||
values[3] | 92 | 1 | T114 | 8 | T115 | 2 | T116 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 448324165 | 1 | T1 | 4 | T2 | 146224 | T3 | 579708 | ||||
auto[TlIntgErrCmd] | 104 | 1 | T114 | 7 | T115 | 3 | T116 | 4 | ||||
auto[TlIntgErrData] | 78 | 1 | T114 | 6 | T115 | 3 | T116 | 1 | ||||
auto[TlIntgErrBoth] | 88 | 1 | T114 | 7 | T115 | 4 | T116 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |