Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263278824

1

T1

3

T2

67643

T3

289203

full_word

185045611

1

T1

1

T2

78581

T3

290505

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448324165	1			T1	4		T2	146224		T3	579708
auto[TlIntgErrCmd]	104	1			T114	7		T115	3		T116	4
auto[TlIntgErrData]	78	1			T114	6		T115	3		T116	1
auto[TlIntgErrBoth]	88	1			T114	7		T115	4		T116	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230830208

1

T1

1

T2

105233

T3

346900

auto[1]

217494227

1

T1

3

T2

40991

T3

232808

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159441861	1			T1	1		T2	49013		T3	285769
auto[TlIntgErrNone]	partial	auto[1]	103836720	1			T1	2		T2	18630		T3	3434
auto[TlIntgErrNone]	full_word	auto[0]	71388246	1			T2	56220		T3	61131		T4	49140
auto[TlIntgErrNone]	full_word	auto[1]	113657338	1			T1	1		T2	22361		T3	229374
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T114	1		T115	1		T146	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T114	5		T115	2		T116	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T114	1		T169	1		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T169	1		T171	1		T172	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T114	4		T115	1		T146	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T114	1		T115	1		T146	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T173	1		T172	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T114	1		T115	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T114	3		T115	1		T116	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T114	3		T115	3		T116	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T174	1		T175	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T114	1		T146	1		T166	2