Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_app_intf.u_appid_arb	95.05	87.50	92.68			100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_appid_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	87.50	92.68			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.40	98.92	89.47		100.00	98.59	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		32	28	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	0	0.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	3	3
87	0	3
89	3	3
97	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	0	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	41	38	92.68
Logical	41	38	92.68
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Unreachable
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T2,T4,T7

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T2,T4,T7

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T5

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T5

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Not Covered
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T7
1	1	Not Covered

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T2,T4,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	1026	1026	0	0
GntImpliesReady_A	2147483647	6923	0	0
GntImpliesValid_A	2147483647	6923	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	6923	0	0
NoReadyValidNoGrant_A	2147483647	2147483647	0	0
Priority_A	2147483647	2873946	0	0
ReadyAndValidImplyGrant_A	2147483647	6923	0	0
ReqAndReadyImplyGrant_A	2147483647	6923	0	0
ReqImpliesValid_A	2147483647	2873946	0	0
ValidKnown_A	2147483647	2147483647	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1051	951	0	0
T2	641670	641612	0	0
T3	127388	127382	0	0
T4	981304	981231	0	0
T5	34163	34090	0	0
T6	630281	630273	0	0
T7	225950	225892	0	0
T11	202859	202853	0	0
T12	203560	203503	0	0
T13	1116	958	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6923	0	0
T2	641670	84	0	0
T3	127388	0	0	0
T4	981304	8	0	0
T5	34163	7	0	0
T6	630281	0	0	0
T7	225950	37	0	0
T8	0	10	0	0
T11	202859	0	0	0
T12	203560	0	0	0
T13	1116	0	0	0
T14	0	19	0	0
T15	0	19	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	140957	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6923	0	0
T2	641670	84	0	0
T3	127388	0	0	0
T4	981304	8	0	0
T5	34163	7	0	0
T6	630281	0	0	0
T7	225950	37	0	0
T8	0	10	0	0
T11	202859	0	0	0
T12	203560	0	0	0
T13	1116	0	0	0
T14	0	19	0	0
T15	0	19	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	140957	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1051	951	0	0
T2	641670	641612	0	0
T3	127388	127382	0	0
T4	981304	981231	0	0
T5	34163	34090	0	0
T6	630281	630273	0	0
T7	225950	225892	0	0
T11	202859	202853	0	0
T12	203560	203503	0	0
T13	1116	958	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1051	951	0	0
T2	641670	641612	0	0
T3	127388	127382	0	0
T4	981304	981231	0	0
T5	34163	34090	0	0
T6	630281	630273	0	0
T7	225950	225892	0	0
T11	202859	202853	0	0
T12	203560	203503	0	0
T13	1116	958	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6923	0	0
T2	641670	84	0	0
T3	127388	0	0	0
T4	981304	8	0	0
T5	34163	7	0	0
T6	630281	0	0	0
T7	225950	37	0	0
T8	0	10	0	0
T11	202859	0	0	0
T12	203560	0	0	0
T13	1116	0	0	0
T14	0	19	0	0
T15	0	19	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	140957	22	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1051	951	0	0
T2	641670	636292	0	0
T3	127388	127382	0	0
T4	981304	980738	0	0
T5	34163	34062	0	0
T6	630281	630273	0	0
T7	225950	216417	0	0
T11	202859	202853	0	0
T12	203560	203503	0	0
T13	1116	621	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2873946	0	0
T2	641670	5320	0	0
T3	127388	0	0	0
T4	981304	493	0	0
T5	34163	28	0	0
T6	630281	0	0	0
T7	225950	9475	0	0
T11	202859	0	0	0
T12	203560	0	0	0
T13	1116	337	0	0
T14	0	2591	0	0
T15	0	76	0	0
T33	0	580	0	0
T35	0	1053	0	0
T38	140957	10752	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6923	0	0
T2	641670	84	0	0
T3	127388	0	0	0
T4	981304	8	0	0
T5	34163	7	0	0
T6	630281	0	0	0
T7	225950	37	0	0
T8	0	10	0	0
T11	202859	0	0	0
T12	203560	0	0	0
T13	1116	0	0	0
T14	0	19	0	0
T15	0	19	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	140957	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6923	0	0
T2	641670	84	0	0
T3	127388	0	0	0
T4	981304	8	0	0
T5	34163	7	0	0
T6	630281	0	0	0
T7	225950	37	0	0
T8	0	10	0	0
T11	202859	0	0	0
T12	203560	0	0	0
T13	1116	0	0	0
T14	0	19	0	0
T15	0	19	0	0
T33	0	1	0	0
T35	0	6	0	0
T38	140957	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2873946	0	0
T2	641670	5320	0	0
T3	127388	0	0	0
T4	981304	493	0	0
T5	34163	28	0	0
T6	630281	0	0	0
T7	225950	9475	0	0
T11	202859	0	0	0
T12	203560	0	0	0
T13	1116	337	0	0
T14	0	2591	0	0
T15	0	76	0	0
T33	0	580	0	0
T35	0	1053	0	0
T38	140957	10752	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1051	951	0	0
T2	641670	641612	0	0
T3	127388	127382	0	0
T4	981304	981231	0	0
T5	34163	34090	0	0
T6	630281	630273	0	0
T7	225950	225892	0	0
T11	202859	202853	0	0
T12	203560	203503	0	0
T13	1116	958	0	0